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LPSPI 8 32bit words in one frame S32K142

Question asked by Brian Flinn on Oct 24, 2019
Latest reply on Nov 4, 2019 by Daniel Martynek

Need to configure S32K142 LPSPI to talk to NXP NJJ29C2 LF driver chip 8 32bit words in one frame.


Hello I need to configure S32K142 LPSPI to talk to NXP NJJ29C2 LF driver.


It requires a SPI single frame with 256 bits i.e. 8 32bit words..


I have attempted to configure the LPSPI on our S32K142 as shown below... and it does not work.


It starts transmission and does have a neg going CS and sends out 6 32bit words nad then does not send anymore.


It does finish the for loop in the TX shown below, i.e. it is not hung waiting for the LPSPI_SR_TDF_MASK, it simply does not send any more data after the 6th 32bit word, also no sclk after the 6th 32bit word, and CS is and stays asserted low forever.

 

Please advise on how you are using S32K142 to talk to NJJ29C2, and or example code, and or fixes to my configuration etc.

 

After we get through the data sending I will need to know how to receive the 8 32bit words from the NJJ29C2

 

The LSSPI setup --- 

void LPSPI1_init_master(void)
{
PCC->PCCn[PCC_LPSPI1_INDEX] = 0; /* Disable clocks to modify PCS ( default) */

PCC->PCCn[PCC_LPSPI1_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */

LPSPI1->CR = 0x00000000; /* Disable module for configuration */

LPSPI1->IER = 0x00000000; /* Interrupts not used */

LPSPI1->DER = 0x00000000; /* DMA not used */

LPSPI1->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */

LPSPI1->CFGR1 = 0x00000001; /* Configurations: master mode*/
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */

LPSPI1->TCR = 0x800000FF; // for 256 bits in one frame i.e. 8 32bit words
/* CPOL=1: SCK inactive state is high */
/* CPHA=0: Data is captured on the leading edge of SCK and changed on the following edge of SCK*/
/* PRESCALE=2: Functional clock divided by 2**2 = 4 */
/* PCS=0: Transfer using PCS0 */
/* LSBF=0: Data is transferred MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=256: # bits in frame = 255+1=256 */

 

LPSPI1->CCR = 0x04090808; /* Clk dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
LPSPI1->FCR = 0x00000003; /* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI1->CR = 0x00000009; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
}
//----------------------------------------------------------------------------


// the TX
for(i= 0; i < 8; i++)
{
send = xmit_array[i];

while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI1->TDR = send; /* Transmit data */
LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

 

Thank You

Brian

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