Why i.MX8M Mini EVK use seperate clock for REFCLK_N/P instead of PCIE_CLK_N/P from SoC

[m_c]

In 8MMINILPD4-EVK, it uses 9FGV0241AKLF to generate clock for REFCLK_N/P of M.2 connector.

Why use PCIE_CLK_N/P (A21/B21) from i.MX8 Mini directly?

[inderjitbains]

How bad is the jitter on the internal clock?  Is it still within the PCIE spec?  Has anyone used the internal clock successfully? 

[Yuri · Accepted solution]

Hello,

   According to section 3.8 (PCIE connectivity) of Hardware Development Guide for the i.MX8Mm:
 
The i.MX 8M Mini has one PCIE interface. There is a pair of pins with the name of PCIE _CLK_P/N. These pins are bi-directional which can either be used to feed 100 MHz reference clock to the PHY from external clock source, or to output an internal generated 100 MHz reference clock to PCIE connector or PCIE device.
On EVK, a PCIE clock generator chip (9FGV0241) is used to feed high-quality clock to both the PHY and connecter/device. If a PCIE clock generator is not available, use the internal clock of the chip. Note that the internal clock exhibits larger jitter than that from PCIE clock generator

https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG 

Have a great day,
Yuri

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