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LCDIF 8bits bus-width interface to 24 bits LCD display on IMX6UL

Question asked by Henri Koch on Sep 23, 2019
Latest reply on Sep 27, 2019 by igorpadykov



I am currently working with the imx6ul and I need to configure the mxsfb driver that supports the eLCDIF controller to enable the use of 8 bits bus-width with 24 bits RGB pixels.


My configuration is:

  • imx6Ultralite,
  • LCD 320x240 24 bits RGB display connected to the first LCD_DATA pins (0-7),
    • tested with the 24 bits bus-width and it is working fine
  • DOTCLK mode is used (HSYNC + VSYNC + DATA ENABLE) and NOT MPU 8080 or i80.


The current driver supports the 24 bits pixels to 24 bits bus-width but as shown in the image hereafter, the 8 bits mode of the display requires to output R, G and B on the same LCD pins one after the other. In order to do that, the LCD display needed PXL_CLK increases from 6 MHz to 26 MHz.



Display timings


I increased the PXL_CLK directly in the CCM to 26 MHz and configured the register of the eLCDIF with the following values:



I have also tried to modify other registers related to timing, but the reference manual is not clear in the relationship between all timing registers and no graphs are provided to get an overview.


Any help with a guidance towards which register should be modified to make it works ?


Thank you !