K82 : QSPI reduce clock in case of write operation.

[EugeneHiihtaja]

Hello !

In qspi example, while write operation, qspi clock reduced twice as usually :

#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Reduce frequency while clock divider is less than 2 */
bool isDivNeedRestore = false;
uint8_t qspiClockDiv = ((BOARD_QSPI->MCR & QuadSPI_MCR_SCLKCFG_MASK) >> QuadSPI_MCR_SCLKCFG_SHIFT) + 1U;
if (qspiClockDiv == 1U)
{
/* Reduce the frequency */
isDivNeedRestore = true;
QSPI_Enable(BOARD_QSPI, false);
BOARD_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
BOARD_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(1U);
QSPI_Enable(BOARD_QSPI, true);
}
#endif

.....

WRITE

........

#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Restore the frequency if needed */
if (isDivNeedRestore)
{
QSPI_Enable(BOARD_QSPI, false);
BOARD_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
BOARD_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(0U);
QSPI_Enable(BOARD_QSPI, true);
}
#endif

QSPI clock is defined like #define QSPI_CLK_FREQ         CLOCK_GetFreq(kCLOCK_McgPll0Clk)

and it equal to 120Mhz.

From MX25 QSPI memory spec ( used on FRDM K82 board ) I can see :

"- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz"

What is reason for reduce/restore  QSPI clock ?

How to calculate external SPI clock in this case ?

Regards,

Eugene

[FelipeGarcia]

Hello Eugene,

I copied the following text from the readme file that I believe it can be useful for you.

Notice: While do program, it is not suggested to make the flash write frequency bigger than the core clock frequency.

In some tool chain's Debug version, this may cause core do not have enough speed to send data to flash.

The flash write frequency equals to QSPI working frequency plus data line number. For example, if QSPI working in 48MHz,

program command uses quad mode, the write frequency is 48MHz * 4 = 192MHz.

If you have further question, please let me know.

I hope this helps,

Have a great day,
Felipe

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[EugeneHiihtaja]

Hello Felipe !

Can be look our configuration in more details. Chapter 6.7.12 QuardSPI clocking is not so transparent.

I'm using 

/* Set clock source to kCLOCK_CoreSysClk */
config.clockSource = 0U; // 120 Mhz

And enable quad mode.

How in this case I can understand RM notice:

"

"The controller supports singles,dual,
quad or octal data lines in single (SDR) or double (DDR) data rate configurations. SDR
mode supports upto 100 MHz and DDR mode supports up to 75MHz.

"

So this is External QuadSPI clock limit ?  Not clock source limit ?

In this case in case of write I should drop Internal reference clock to 120Mhz from 480Mhz what is applicable for read operation.

In this case QuadSPIx_MCR[27:24] divider should be 4  ( value in register 3.). Is this so ?

But in example :

/* Reduce frequency while clock divder is less than 2 */
uint8_t qspiClockDiv = ((EXAMPLE_QSPI->MCR & QuadSPI_MCR_SCLKCFG_MASK) >> QuadSPI_MCR_SCLKCFG_SHIFT) + 1U;
if (qspiClockDiv == 1U)
{
/* Reduce the frequency */
isDivNeedRestore = true;
QSPI_Enable(EXAMPLE_QSPI, false);
EXAMPLE_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
EXAMPLE_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(1U);
QSPI_Enable(EXAMPLE_QSPI, true);
}

Value is 1 and divider will be 2 not 4.

Or what this divider should be If I'm using SystemClock 120Mhz as clock source for QSPI controller ?

What will be external QuardSPI clock in this case ?

Regards,

Eugene

[FelipeGarcia]

Hello Eugene,

If you load the example provided in the SDK you can see the following behavior:

In QSPI_Init function, you can see that the SDK configures the divider by 5 with the following code.

    /* To avoid the configured baudrate exceeds the expected baudrate value, which may possibly put the

    QSPI work under unsupported frequency, set the divider higher when there is reminder, use ceiling

    operation, ceiling(a/b) = (a-1)/b + 1. */

    val |= QuadSPI_MCR_SCLKCFG((srcClock_Hz - 1) / config->baudRate);

    base->MCR = val;

Then, when you get to the program function there is no need to reduce the frequency.

Regarding your question, you are correct, if you are using 120 MHz as the QSPI clock with no dividers, then you should reduce the frequency by 2 in order to ensure the correct behavior of flash writing.

I hope this helps.

Best regards,

Felipe

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[EugeneHiihtaja]

Hi Felipe !

After initialization register has value QSPI0 MCR 0x040F000C and clock divider is 4 there. DDR is not enabled.

It means External QuardSPI clock is 30Mhz.

Is this so ?

Regards,

Eugene

[FelipeGarcia]

Hello Eugene,

Yes, that is correct. Please check snippet attached from reference manual chapter 6.7.12.

Best regards,

Felipe

[EugeneHiihtaja]

Hi Felipe !

Thank you !

It mean that text in RM 

"The controller supports singles,dual,
quad or octal data lines in single (SDR) or double (DDR) data rate configurations. SDR
mode supports upto 100 MHz and DDR mode supports up to 75MHz.

"

is talking about ExternalQuadSPI clock or clock what should be visible after Clock Divider.

Is this so ?

Regards,

Eugene

[FelipeGarcia · Accepted solution]

Hello Eugene,

Please check the following extract from the reference manual.

DDR mode of the QuadSPI requires a 4x, 2x, and 1x internal reference clock. In DDR mode, the clock divider output is used as the 4x internal reference clock. The 2x and 1x clocks are divided down from that clock.

To generate the maximum 75Mhz flash frequency supported in DDR mode, MCGPLL2XCLK should be 300MHz with QuadSPIx_MCR[SCLKCFG]=0 to generate the 4x internal clock required.

This means the following example:

Hope it helps!

 
Have a great day,
Felipe

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