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K82 : QSPI reduce clock in case of write operation.

Question asked by Eugene Hiihtaja on Aug 27, 2019
Latest reply on Sep 3, 2019 by Felipe García

Hello !

 

In qspi example, while write operation, qspi clock reduced twice as usually :

 

#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Reduce frequency while clock divider is less than 2 */
bool isDivNeedRestore = false;
uint8_t qspiClockDiv = ((BOARD_QSPI->MCR & QuadSPI_MCR_SCLKCFG_MASK) >> QuadSPI_MCR_SCLKCFG_SHIFT) + 1U;
if (qspiClockDiv == 1U)
{
/* Reduce the frequency */
isDivNeedRestore = true;
QSPI_Enable(BOARD_QSPI, false);
BOARD_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
BOARD_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(1U);
QSPI_Enable(BOARD_QSPI, true);
}
#endif

.....

WRITE

........

 

#if !defined(FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Restore the frequency if needed */
if (isDivNeedRestore)
{
QSPI_Enable(BOARD_QSPI, false);
BOARD_QSPI->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
BOARD_QSPI->MCR |= QuadSPI_MCR_SCLKCFG(0U);
QSPI_Enable(BOARD_QSPI, true);
}
#endif

 

 

QSPI clock is defined like #define QSPI_CLK_FREQ         CLOCK_GetFreq(kCLOCK_McgPll0Clk)

and it equal to 120Mhz.

 

From MX25 QSPI memory spec ( used on FRDM K82 board ) I can see :

 

"- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz"

 

What is reason for reduce/restore  QSPI clock ?

 

How to calculate external SPI clock in this case ?

 

Regards,

Eugene

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