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DDR calibration issue on a custom iMX6Solo board

Question asked by Michael Novotnuy on Jun 27, 2019
Latest reply on Jul 2, 2019 by Mark Middleton

#Mark Middleton 

 

I'm trying to make DDR calibration on my custom iMX6 board. DDR memory chip is IS43TR16128B-125KBL.

I used MX6DL_SabreSD_DDR3_register_programming_aid_v2.2.xlsx as a reference to create registers settings.

For calibration I tried DDR_Stress_Tester_V1.0.2, DDR_Stress_Tester_V1.0.3 and ddr_stress_tester_v3.00

version 1.0.2 and 1.0.3 got the same result as in my comment

version 3.0.0 result:

============================================
        DDR Stress Test (3.0.0)
        Build: Dec 14 2018, 14:12:28
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x20000001
============================================

ARM Clock set to 800MHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Temperature: 44
============================================

DDR Freq: 396 MHz

 

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
  MPWLHWERR register read out for factory diagnostics:
  MPWLHWERR PHY0 = 0x00000000

 

HW WL cal status: no suitable delay value found for byte 0

HW WL cal status: no suitable delay value found for byte 1

HW WL cal status: no suitable delay value found for byte 2

HW WL cal status: no suitable delay value found for byte 3
Write leveling calibration completed but failed, the following results were found:
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
Write DQS delay result:
   Write DQS0 delay: 31/256 CK
   Write DQS1 delay: 31/256 CK
   Write DQS2 delay: 31/256 CK
   Write DQS3 delay: 31/256 CK

 

Error: failed during write leveling calibration

 

It is my first experience with iMX6 processors and DDR calibration.

My .xlsx file and DDR schematic are attached.

 

Thanks

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