I'm interested in connecting two devices to the same SPI bus which differ on the idle clock polarity (defined as CPOL).
The MPC5744P i'm working on provides a clever resource to deal with this, which are the CTAR registers and the CTAS field when performing a TX write.
However, I have a question I've been unable to answer reading through the documentation.
If transfer #0 is made to CS0 with CPOL=0 (using CTAR0 config), and then transfer #1 is made to CS1 with CPOL=1 (using CTAR1 config):
a) Clock polarization change happens before CS assert (ideal)
b) Clock polarization change happens after CS assert (unfeasible, as the clock change may count as a valid shift)
Please provide me with evidence on documentation of either answer, as this will condition my entire design.