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Resetting LPC546xx while writing to external static RAM

Question asked by Viggo Joergensen on Feb 15, 2019
Latest reply on Feb 18, 2019 by xiangjun.rong

Hi there,


ref. LPC546xx datasheet fig.25 External static memory read/write access


Does a low on the reset pin abort an external write cycle - if going low in the WR5 window - with a chance for leaving garbage in the addressed SRAM location?


Or will the reset action be delayed until the writecycle has finished?


Just short - is the action of a low reset asynchronous or synchronous with what the CPU is actually doing.


Best regards