ref. LPC546xx datasheet fig.25 External static memory read/write access
Does a low on the reset pin abort an external write cycle - if going low in the WR5 window - with a chance for leaving garbage in the addressed SRAM location?
Or will the reset action be delayed until the writecycle has finished?
Just short - is the action of a low reset asynchronous or synchronous with what the CPU is actually doing.