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failed during write leveling calibration

Question asked by vinothkumar s on Feb 14, 2019
Latest reply on May 29, 2019 by vinothkumar s

Hi All,

 

   I am testing a new hardware using i.MX6 solo interfaced with DDR3 by running DDR stress test v2.60 tool and it's failed during calibration and I got error.

 

Please see debug message as following:

 

Normal Boot
Hit any key to stop autoboot:  0
=> dcache off
=> icache off
=> ext4load mmc 0:1 0x907000 ddr-test-uboot-jtag-mx6dl.bin
71812 bytes read in 127 ms (551.8 KiB/s)
=> go 0x907000
## Starting application at 0x00907000 ...

 

============================================
        DDR Stress Test (3.0.0)
        Build: Dec 14 2018, 14:20:16
        NXP Semiconductors.
============================================

 

============================================
        Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
============================================

 

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000040
SRC_SBMR2(0x020d801c) = 0x22000001
============================================

 

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz
ARM Clock set to 800MHz

 

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================

 

Current Temperature: 45
============================================

 

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB  
For maximum supported density (4GB), we can only access up to 3.75GB.  Type 7 to select this
  DDR density selected (MB): 1024

 


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

 


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

 

Calibration will run at DDR frequency 400MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
  Please enter the MR1 value on the initilization script
  This will be re-programmed into MR1 after write leveling calibration
  Enter as a 4-digit HEX value, example 0004, then hit enter
0004DDR Freq: 396 MHz

 

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
  MPWLHWERR register read out for factory diagnostics:
  MPWLHWERR PHY0 = 0x00000000

 


HW WL cal status: no suitable delay value found for byte 0

 

HW WL cal status: no suitable delay value found for byte 1

 

HW WL cal status: no suitable delay value found for byte 2

 

HW WL cal status: no suitable delay value found for byte 3
Write leveling calibration completed but failed, the following results were found:
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
Write DQS delay result:
   Write DQS0 delay: 31/256 CK
   Write DQS1 delay: 31/256 CK
   Write DQS2 delay: 31/256 CK
   Write DQS3 delay: 31/256 CK

 


Error: failed during write leveling calibration

 

Regards,

VinothS

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