I need to know if SRAM data is retained during any or all of the low power modes:
WAIT, DOZE, STOP.
MCF52235RM Rev. 5 09/2007 (22.214.171.124)
states that the SRAM is disabled in low power modes.
I understand that to mean no read or write access.
It does not say whether data is retained.
Can anyone verify if SRAM data written prior to entering a low power mode
is valid after a return to run mode?
previously posted in Codewarrior forum-oops
My Apologies for that.