Tim Maloy

SRAM Data retention in low power modes

Discussion created by Tim Maloy on Jan 12, 2009
Latest reply on Jan 13, 2009 by Tim Maloy
I need to know if SRAM data is retained during any or all of the low power modes:
WAIT, DOZE, STOP.
 
MCF52235RM  Rev. 5  09/2007 (9.4.2.2)
states that the SRAM is disabled in low power modes.
I understand that to mean no read or write access.
It does not say whether data is retained.
 
Can anyone verify if SRAM data written prior to entering a low power mode
is valid after a return to run  mode?
 
previously posted in Codewarrior forum-oops
My Apologies for that.

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