I'm working I2C device driver on P2020 platform with 400MHz CCB clock. The I2C controller 0 is act as master, and should be configured with 100K/400K/3.4M SCL frequency. But I have problem to get 3.4MHz SCL frequency.
According to P2020 reference manual, AN2919 should be referred to do the configuration (Refer to application note AN2919, "Determining the I2C Frequency Divider Ratio for SCL," for additional guidance regarding the proper use of I2CFDR and I2CDFSRR).
Theoretically, frequency divider is calculated by (CCB clock/2) /(SCL Freq). For given CCB clock, the larger is SCL Frequency, the less is frequency divider.
in order to get 3.4MHz frequency, the frequency divider should be:
(CCB clock/2) / 3.4 = (400 / 2) / 3.4 = 58
But according to AN2919, The following equation is used to calculate the frequency divider:
Frequency divider = B × [A + (floor(3 × C ÷ B) ×2)] ...... (1)
The minimum frequency divider calculated by (1) should be the minimum value of B multiply the minimum value of A. Based on Table 5 of AN2919, the minimum value of B is 16, and the minimum value of A is 10. So the minimum frequency divider calculated by (1) is 16x10=160. It's much more than 58. As for the given CCB clock, the actual SCL frequency for 160 frequency divider is (400/2)/160 = 1.25 (Mhz). It's much less than 3.4M.
Is there any way to get 3.4M SCL frequency?
Thanks for your comments!