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DDR Stress Test Tool on the iMX6ULEVK via JTAG again.

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DDR Stress Test Tool on the iMX6ULEVK via JTAG again.

‎12-10-2018 12:40 AM
1,889 Views
titggtu
Contributor II

I'd like to run the DDR Stress Test Tool on the iMX6ULEVK via JTAG using Segger JLink.

I modified the EVK hardware (removed R1407, R1431 to R1434 and added R1912 and R1914 to R1916).

I initialize a connection with JLink.exe and the commands:

device MCIMX6Y2 (MPU on my EVK MCIMX6Y2DVM09AA)

connect

Type "connect" to establish a target connection, '?' for help

J-Link>connect

Please specify device / core. <Default>: MCIMX6Y2

Type '?' for selection dialog

Device>

Please specify target interface:

  1. J) JTAG (Default)
  2. S) SWD
  3. T) cJTAG

TIF>j

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect

JTAGConf>

Specify target interface speed [kHz]. <Default>: 4000 kHz

Speed>

Device "MCIMX6Y2" selected.

 

Connecting to target via JTAG

Executing J-Link script file function: ConfigTargetSettings()

_____________J-Link script: Setting up AP map__________________

TotalIRLen = 13, IRPrint = 0x0101

*************************

WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

**************************

JTAG chain detection found 3 devices:

 #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP

 #1 Id: 0x00000001, IRLen: 05, Unknown device

 #2 Id: 0x088C101D, IRLen: 04, JTAG-DP

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[1]: APB-AP (IDR: Not set)

Using preconfigured AP[1] as APB-AP

AP[1]: APB-AP found

ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-001BB961 TMC

ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-004BB906 CTI

ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU

ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID:04-001BB101 TSG

ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID:04-000BB4A7 ROM Table

ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID:04-005BBC07 Cortex-A7

Found Cortex-A7 r0p5

6 code breakpoints, 4 data breakpoints

Debug architecture ARMv7.1

Data endian: little

Main ID register: 0x410FC075

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way

D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way

Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way

System control register:

  Instruction endian: little

  Level-1 instruction cache enabled

  Level-1 data cache disabled

  MMU disabled

  Branch prediction enabled

Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Legacy_stop_mode

Clock Init Done

DDR Init Done

Memory zones:

  [0]: Default (Default access mode)

  [1]: AHB-AP (AP0) (DMA like acc. in AP0 addr. space)

  [2]: APB-AP (AP1) (DMA like acc. in AP1 addr. space)

Cortex-A7 identified.

J-Link>

 

J-Link script initializes CLK and DDR, in accordance with the example script provided in EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2.ink.

Then I load the ddr-test-uboot-jtag-mx6ull.bin image using the loadbin command at address 0x00907000.

I connected the COM1 port to the computer and made sure that it was working by sending data to the UART Transmitter Register (UART1_UTXD) register.

 

Next, I have to run the downloaded image for execution.

First question: How to do it right?

The second question is: Should MUU and Level-1 data cache be enabled?

In my case they are off.

«System control register:

  Instruction endian: little

  Level-1 instruction cache enabled

  Level-1 data cache disabled

  MMU disabled

  Branch prediction enabled»

But boot eFUSE   BT_MMU_DISABLE – installed to 0.

J-Link script initializes CLK and DDR attached.

Thanks, Alexey.

Labels (2)
Labels
NXP_iMX6ULL.JLinkScript.zip
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4 Replies

‎01-02-2019 04:04 AM
1,390 Views
titggtu
Contributor II

I found a solution to my problem. To run the test, it is necessary to reset the processor correctly.

See ARM Architecture Reference Manual section A2.6.2 Reset:

A2.6.2 Reset
When the Reset input is asserted on the processor, the ARM processor immediately stops execution of the
current instruction. When Reset is de-asserted, the following actions are performed:

 

 

R14_svc

= UNPREDICTABLE value

 

SPSR_svc = UNPREDICTABLE value
CPSR[4:0] = 0b10011

/* Enter Supervisor mode */
/* Execute in ARM state */
/* Disable fast interrupts */
/* Disable normal interrupts */
/* Disable Imprecise Aborts (v6 only) */

 

CPSR[5]
CPSR[6]
CPSR[7]
CPSR[8]

= 0
= 1
= 1
= 1

 

 

 

Next, I provide a log of the connection with the i.MX 6ULL EVK debug board.

SEGGER J-Link Commander V6.40 (Compiled Oct 26 2018 15:06:29)

DLL version V6.40, compiled Oct 26 2018 15:06:02

 

Connecting to J-Link via USB...O.K.

Firmware: J-Link V10 compiled Oct 26 2018 12:04:17

Hardware version: V10.10

S/N: XXXXXXXX

License(s): FlashBP, GDB

OEM: SEGGER

VTref=3.317V

 

Type "connect" to establish a target connection, '?' for help

J-Link>connect

Please specify device / core. <Default>: MCIMX6Y2

Type '?' for selection dialog

Device>

Please specify target interface:

  1. J) JTAG (Default)
  2. S) SWD
  3. T) cJTAG

TIF>

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect

JTAGConf>

Specify target interface speed [kHz]. <Default>: 4000 kHz

Speed>

Device "MCIMX6Y2" selected.

Connecting to target via JTAG

Executing J-Link script file function: ConfigTargetSettings()

_____________J-Link script: Setting up AP map_____________

TotalIRLen = 13, IRPrint = 0x0101

**************************

WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

**************************

JTAG chain detection found 3 devices:

 #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP

 #1 Id: 0x00000001, IRLen: 05, Unknown device

 #2 Id: 0x088C101D, IRLen: 04, JTAG-DP

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[1]: APB-AP (IDR: Not set)

Using preconfigured AP[1] as APB-AP

AP[1]: APB-AP found

ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-001BB961 TMC

ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-004BB906 CTI

ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU

ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID:04-001BB101 TSG

ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID:04-000BB4A7 ROM Table

ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID:04-005BBC07 Cortex-A7

Found Cortex-A7 r0p5

6 code breakpoints, 4 data breakpoints

Debug architecture ARMv7.1

Data endian: little

Main ID register: 0x410FC075

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way

D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way

Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way

System control register:

  Instruction endian: little

  Level-1 instruction cache enabled

  Level-1 data cache disabled

  MMU disabled

  Branch prediction enabled

Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Stop_mode

/*Run the script and initialize the CLK and DDR3 */

Clock Init Done

DDR Init Done

Memory zones:

  [0]: Default (Default access mode)

  [1]: AHB-AP (AP0) (DMA like acc. in AP0 addr. space)

  [2]: APB-AP (AP1) (DMA like acc. in AP1 addr. space)

Cortex-A7 identified.

J-Link>h

PC: (R15) = 0000883C, CPSR = 400001F3 (SVC mode, THUMB FIQ dis. IRQ dis.)

Current:

     R0 =00002040, R1 =00900A30, R2 =10000000, R3 =00000800

     R4 =00000000, R5 =00000002, R6 =00900BA4, R7 =02020000

     R8 =00008840, R9 =00008840, R10=021E8000, R11=0001C200, R12=000100A1

     R13=00020200, R14=020E0014, SPSR=0091FF64

USR: R8 =021E8000, R9 =0001C200, R10=000100A1, R11=00020200, R12=020E0014

     R13=B08071EC, R14=9410365C

FIQ: R8 =145A4BAC, R9 =13E07390, R10=28E18AA4, R11=82091972, R12=94128C58

     R13=34957FE8, R14=67C0680F, SPSR=8101005D

IRQ: R13=2D235DD0, R14=F46B68C4, SPSR=A0030921

SVC: R13=0091FF64, R14=000085E5, SPSR=000001D3

ABT: R13=3B0D2E20, R14=100340EC, SPSR=C1000438

UND: R13=B30D98D8, R14=AE1A2C3B, SPSR=22040E62

/*Reset the CPCR register in accordance with the documentation.*/

J-Link>wreg CPSR 0x000001d3

CPSR = 0x000001D3

J-Link>regs

PC: (R15) = 0000883C, CPSR = 000001D3 (SVC mode, ARM FIQ dis. IRQ dis.)

Current:

     R0 =00002040, R1 =00900A30, R2 =10000000, R3 =00000800

     R4 =00000000, R5 =00000002, R6 =00900BA4, R7 =02020000

     R8 =00008840, R9 =00008840, R10=021E8000, R11=0001C200, R12=000100A1

     R13=00020200, R14=020E0014, SPSR=0091FF64

USR: R8 =021E8000, R9 =0001C200, R10=000100A1, R11=00020200, R12=020E0014

     R13=B08071EC, R14=9410365C

FIQ: R8 =145A4BAC, R9 =13E07390, R10=28E18AA4, R11=82091972, R12=94128C58

     R13=34957FE8, R14=67C0680F, SPSR=8101005D

IRQ: R13=2D235DD0, R14=F46B68C4, SPSR=A0030921

SVC: R13=0091FF64, R14=000085E5, SPSR=000001D3

ABT: R13=3B0D2E20, R14=100340EC, SPSR=C1000438

UND: R13=B30D98D8, R14=AE1A2C3B, SPSR=22040E62

/*load the bin file into memory at 0x00907000*/

J-Link>loadbin ddr-test-uboot-jtag-mx6ull.bin 0x00907000

Downloading file [ddr-test-uboot-jtag-mx6ull.bin]...

O.K.

/*Install a PC to this address and start the processor*/

J-Link>setPC 0x00907000

J-Link>g

J-Link>

After starting the processor, a memory test is started in the console.

DDR_sterss_test.PNG

I think the problem is solved.

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‎12-14-2018 12:02 AM
1,390 Views
titggtu
Contributor II

Hello,

Thanks for the help I will try.

I use version V6.40 of the J-Link software.
i.MX6/7 DDR Stress Test Tool V3.00 behaves exactly the same as V2.92.
Are there any other solutions to the problem?

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‎12-13-2018 11:57 PM
1,390 Views
Yuri
NXP Employee
NXP Employee

Hello,

  Please try the recent DDR test version

https://community.nxp.com/docs/DOC-105652 

Regards,

Yuri.

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‎12-13-2018 11:26 PM
1,390 Views
Yuri
NXP Employee
NXP Employee

Hello,

  Following forum states about issues with i.MX 6UL, that was resolved in

in version 6.14c of the SEGGER - The Embedded Experts - Downloads - J-Link / J-Trace 

[SOLVED] I.MX6UL support in segger j-link probe - J-Link/Flasher related - SEGGER - Forum 


Have a great day,
Yuri

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