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DDR Stress Test Tool on the iMX6ULEVK via JTAG again.

Question asked by Alexey Tsitou on Dec 10, 2018
Latest reply on Jan 2, 2019 by Alexey Tsitou

I'd like to run the DDR Stress Test Tool on the iMX6ULEVK via JTAG using Segger JLink.

I modified the EVK hardware (removed R1407, R1431 to R1434 and added R1912 and R1914 to R1916).

I initialize a connection with JLink.exe and the commands:

device MCIMX6Y2 (MPU on my EVK MCIMX6Y2DVM09AA)

connect

Type "connect" to establish a target connection, '?' for help

J-Link>connect

Please specify device / core. <Default>: MCIMX6Y2

Type '?' for selection dialog

Device>

Please specify target interface:

  1. J) JTAG (Default)
  2. S) SWD
  3. T) cJTAG

TIF>j

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect

JTAGConf>

Specify target interface speed [kHz]. <Default>: 4000 kHz

Speed>

Device "MCIMX6Y2" selected.

 

Connecting to target via JTAG

Executing J-Link script file function: ConfigTargetSettings()

_____________J-Link script: Setting up AP map__________________

TotalIRLen = 13, IRPrint = 0x0101

*************************

WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

**************************

JTAG chain detection found 3 devices:

 #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP

 #1 Id: 0x00000001, IRLen: 05, Unknown device

 #2 Id: 0x088C101D, IRLen: 04, JTAG-DP

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[1]: APB-AP (IDR: Not set)

Using preconfigured AP[1] as APB-AP

AP[1]: APB-AP found

ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-001BB961 TMC

ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID:04-004BB906 CTI

ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID:04-004BB912 TPIU

ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID:04-001BB101 TSG

ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID:04-000BB4A7 ROM Table

ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID:04-005BBC07 Cortex-A7

Found Cortex-A7 r0p5

6 code breakpoints, 4 data breakpoints

Debug architecture ARMv7.1

Data endian: little

Main ID register: 0x410FC075

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way

D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way

Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way

System control register:

  Instruction endian: little

  Level-1 instruction cache enabled

  Level-1 data cache disabled

  MMU disabled

  Branch prediction enabled

Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Legacy_stop_mode

Clock Init Done

DDR Init Done

Memory zones:

  [0]: Default (Default access mode)

  [1]: AHB-AP (AP0) (DMA like acc. in AP0 addr. space)

  [2]: APB-AP (AP1) (DMA like acc. in AP1 addr. space)

Cortex-A7 identified.

J-Link>

 

J-Link script initializes CLK and DDR, in accordance with the example script provided in EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2.ink.

Then I load the ddr-test-uboot-jtag-mx6ull.bin image using the loadbin command at address 0x00907000.

I connected the COM1 port to the computer and made sure that it was working by sending data to the UART Transmitter Register (UART1_UTXD) register.

 

Next, I have to run the downloaded image for execution.

First question: How to do it right?

The second question is: Should MUU and Level-1 data cache be enabled?

In my case they are off.

«System control register:

  Instruction endian: little

  Level-1 instruction cache enabled

  Level-1 data cache disabled

  MMU disabled

  Branch prediction enabled»

But boot eFUSE   BT_MMU_DISABLE – installed to 0.

 

J-Link script initializes CLK and DDR attached.

 

Thanks, Alexey.

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