I am developing an external JTAG debugger for some NXP products.
For external debug a Reset Catch debug event should be generated when EDECR.RCE = 1 and the processor exits reset state. If halting debug mode is enabled this should cause the processor to enter debug mode.
This does not seem to work for either i.MX8MQ or i.MX6Q.
When I set EDECR.RCE = 1 and do a reset the processor boots (does not break at reset).
When I check the reset state (EDPRSR.R) it actually shows that the processor is in reset state, even though it is booting.
Are there any known issues with external debug reset catch debug events?