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T1040 IFC NOR ADDR Timing

Question asked by Nick Sutch on Sep 19, 2018
Latest reply on Sep 26, 2018 by Nick Sutch

I have read and the Datasheet and Reference Manual for the T1040 IFC interface for NOR Flash - my design uses simple/asynchronous NOR PC28F00BM29EWHA with an external latch. I've created a timing diagram for a burst read cycle much like in Figure 24-39 of the RM but what I can't work out is what governs the address valid periods for ADDR0, ADDR1, ADDR2 etc (Names are in reference to figure 24-39) ??

 

I feel like I need this to make sure the address is valid for long enough at the flash device as well as ensuring the sample point is in the middle of the valid period of the data coming back to the T1040. I can't see in the documents a register setting or paramter for this - or am I misunderstanding somthing?

 

Thanks in advance,

Nick

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