i.MX8M Quad Bord Hangs in SPL

[yashavanthashet]

Hi,

We are using custom board with i.MX8M quad processor and it hangs after SPL boot with below prints.

U-Boot SPL 2017.03-imx_v2017.03_4.9.51_imx8m_ga+g2537522 (Aug 07 2018 - 10:19:03)
PMIC:  PFUZE100 ID=0x10
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training PASS
Training PASS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training PASS
Normal Boot
Trying to boot from MMC2

It wont go further than above prints.

Can anyone let me know the reasons for hanging here.

Thanks in advance.

Best Regards,

Yashavantha

[igorpadykov · Accepted solution]

Hi Yashavantha

reason may be ddr errors so one can run ddr test and rebuild image using

guidelines in Chapter 4 How to bring up a new MX8M board MX8M_DDR_Tool_User_Guide.docx

included in package

i.MX 8M DDR Tool Release 

Best regards
igor
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[yashavanthashet]

Hi Igor,

After applying "0001-ATF-support-to-different-LPDDR4-configurations.patch" patch file mentioned here to ATF source code, issue got resolved.

Thank you.

Regards,

Yashavantha

[yashavanthashet]

Dear Igor,

Thank you for the reply.

We have done DDR calibration and stress test successfully and using the ddr code in uboot which is generated after stress test. Please see below prints.

MX8 DDR Stress Test  

--Set up the MMU and enable I and D cache--
   - This is the Cortex-A53 core
  - Check if I cache is enabled  
  - Enabling I cache since it was disabled  
  - Push base address of TTB to TTBR0_EL3  
  - Config TCR_EL3  
  - Config MAIR_EL3  
  - Enable MMU  
  - Data Cache has been enabled  
  - Check system memory register, only for debug  

   - VMCR Check:
   - ttbr0_el3: 0x91d000
   - tcr_el3: 0x2051c
   - mair_el3: 0x774400
   - sctlr_el3: 0xc01815
   - id_aa64mmfr0_el1: 0x1122

  - MMU and cache setup complete  

*************************************************************************
            ARM clock(CA53) rate: 800MHz
            DDR Clock: 800MHz

============================================
        DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 15, col size: 10
Two chip selects are used  
Number of DDR controllers used on the SoC: 1
Density per chip select:   1024MB  
Density per controller is: 2048MB  
Total density detected on the board is: 2048MB  
============================================

MX8M: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @800Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @334Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @800Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
....[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
  Actual DDR Clock rate being tested:  
  - DRC controller0: 400MHz,  -DDR0 PHY: 800MHz
  --------------------------------  
  --Running DDR test on region 1--  
  --------------------------------  

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test  
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test

Success: DDR Stress test completed!!!

Do you think anything missed out above?

Thanks and regards,

Yashavantha

[igorpadykov]

Hi Yashavantha

is there changes (except memory) in custom board design compared to nxp reference board i.MX8M EVK ?

If not, could you try Demo Image below

https://www.nxp.com/webapp/Download?colCode=L4.9.51_IMX8MQ_GA&appType=license&location=null&Parent_n... 

Best regards
igor
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