I have one question about reference clock(ipp_card_clk_in) frequency of DLL (Delay Line)
if uSDHC is in DDR(dual data rate) mode.
I think that
* 50MHz in SD3.0 DDR mode
* 52MHz in EMMC4.4 DDR mode
So reference clock period of ipp_card_clk_in are
* 20ns = 1/50MHz in SD3.0 DDR mode
* 19.2ns = 1/52MHz in EMMC4.4 DDR mode.
It is not 100 or 104MHz(10 or 9.62nsec) in each DDR mode.
Is it correct?