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CRC_CRC endianness dependent on CRC_CTRL[WAS]?

Question asked by Xaro Wubas on May 13, 2018

I program the Kinetis K60 (little endian) via assembly.

"When programming data values, the values can be written 8 bits, 16 bits, or 32 bits at a
time, provided all bytes are contiguous; with *MSB* of data value written first."

 

When you write the *seed* value to CRC_CRC you MUST NOT reverse the byte order from LSB to MSB.

However, when I write *data* values to CRC_CRC I must reverse it from LSB to MSB.

 

Is that expected behavior?

Does the specification really distinguish between the terms "seed value" and "data value", so that the MSB restriction only applies to "data values"?

Would be quite confusing. Is there a reason?

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