i want to connect my RT1050 to a FPGA via FlexSPI, using Hyberbus.
The max. clock freq is limited to 166 MHz.
Please can you tell me if these calculation is correct:
spi clock freq. 166 MHz => 332 MByte/sec (8 Bit Hyperbus) => DDR mode
The command and address settings takes about 13 Cycles, but the i can read with 332 MByte/sec.
Is this correct?