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RT1050 FlexSPI

Question asked by Christian Gradl on May 7, 2018
Latest reply on May 15, 2018 by Christian Gradl


i want to connect my RT1050 to a FPGA via FlexSPI, using Hyberbus.

The max. clock freq is limited to 166 MHz.

Please can you tell me if these calculation is correct:

spi clock freq. 166 MHz => 332 MByte/sec (8 Bit Hyperbus) => DDR mode

The command and address settings takes about 13 Cycles, but the i can read with 332 MByte/sec.


Is this correct?