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MPC5746C.h 5.0.1 missing CAN buffers

Question asked by Christopher Holland on Mar 20, 2018

Hi,

 

I tried updating the MPC5746C.h file and noticed the message buffers are missing.

CAN_0_MB_tag MB[64];  is not in MPC5746C.h revision 5.0.1.

Seems odd, since revision 4.0.1 seemed to update to the correct number.

It's either that, or I have an edited version. 

I got the version from the following

    MPC5 software example list    

       MPC5746C

            Example MPC5746C PIT ISR GHS614  <-- MPC5746C.h Version 5.0.1

 

* 4.0.1 M.D. 07-JUL-16 -Corrected number of CAN Message *
*                                      Buffers from 64 to 96 b *
* 5.0 I.T. 03-MAY-17 -Generated from updated RDP Rev5

 

I am using MPC57465C.h revision 4.0.0

 

Is there an official repository that I can get the latest and greatest MPC5746C.h file?

 

Thank you,

 

 

/* CAN 4.0.0 TAG ================================================= */

CAN_0_CBT_tag CBT; /* CAN Bit Timing Register */
uint8_t CAN_0_reserved2[44];
CAN_0_MB_tag MB[64];
uint8_t CAN_0_reserved3[1024];
CAN_0_RXIMR_tag RXIMR[64]; /* Rx Individual Mask Registers */

 

/* CAN 5.0.1 TAG ================================================= */

CAN_0_CBT_tag CBT; /* CAN Bit Timing Register */
uint8_t CAN_0_reserved2[44];
CAN_0_RAMn_tag RAMn[384]; /* Embedded RAM */
uint8_t CAN_0_reserved3[512];
CAN_0_RXIMR_tag RXIMR[96]; /* Rx Individual Mask Registers */

 

 

/* CAN 4.0.0 TAG ================================================= */

struct CAN_0_tag {
CAN_0_MCR_tag MCR; /* Module Configuration Register */
CAN_0_CTRL1_tag CTRL1; /* Control 1 register */
CAN_0_TIMER_tag TIMER; /* Free Running Timer */
uint8_t CAN_0_reserved0[4];
CAN_0_RXMGMASK_tag RXMGMASK; /* Rx Mailboxes Global Mask Register */
CAN_0_RX14MASK_tag RX14MASK; /* Rx 14 Mask register */
CAN_0_RX15MASK_tag RX15MASK; /* Rx 15 Mask register */
CAN_0_ECR_tag ECR; /* Error Counter */
CAN_0_ESR1_tag ESR1; /* Error and Status 1 register */
CAN_0_IMASK2_tag IMASK2; /* Interrupt Masks 2 register */
CAN_0_IMASK1_tag IMASK1; /* Interrupt Masks 1 register */
CAN_0_IFLAG2_tag IFLAG2; /* Interrupt Flags 2 register */
CAN_0_IFLAG1_tag IFLAG1; /* Interrupt Flags 1 register */
CAN_0_CTRL2_tag CTRL2; /* Control 2 register */
CAN_0_ESR2_tag ESR2; /* Error and Status 2 register */
uint8_t CAN_0_reserved1[8];
CAN_0_CRCR_tag CRCR; /* CRC Register */
CAN_0_RXFGMASK_tag RXFGMASK; /* Rx FIFO Global Mask register */
CAN_0_RXFIR_tag RXFIR; /* Rx FIFO Information Register */
CAN_0_CBT_tag CBT; /* CAN Bit Timing Register */
uint8_t CAN_0_reserved2[44];
CAN_0_MB_tag MB[64];
uint8_t CAN_0_reserved3[1024];
CAN_0_RXIMR_tag RXIMR[64]; /* Rx Individual Mask Registers */
uint8_t CAN_0_reserved4[384];
CAN_0_CTRL1_PN_tag CTRL1_PN; /* Pretended Networking Control 1 Register */
CAN_0_CTRL2_PN_tag CTRL2_PN; /* Pretended Networking Control 2 Register */
CAN_0_WU_MTC_tag WU_MTC; /* Pretended Networking Wake Up Match Register */
CAN_0_FLT_ID1_tag FLT_ID1; /* Pretended Networking ID Filter 1 Register */
CAN_0_FLT_DLC_tag FLT_DLC; /* Pretended Networking DLC Filter Register */
CAN_0_PL1_LO_tag PL1_LO; /* Pretended Networking Payload Low Filter 1 Register */
CAN_0_PL1_HI_tag PL1_HI; /* Pretended Networking Payload High Filter 1 Register */
CAN_0_FLT_ID2_IDMASK_tag FLT_ID2_IDMASK; /* Pretended Networking ID Filter 2 Register / ID Mask Register */
CAN_0_PL2_PLMASK_LO_tag PL2_PLMASK_LO; /* Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register */
CAN_0_PL2_PLMASK_HI_tag PL2_PLMASK_HI; /* Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register */
uint8_t CAN_0_reserved5[24];
CAN_0_WMB_tag WMB[4];
uint8_t CAN_0_reserved6[128];
CAN_0_FDCTRL_tag FDCTRL; /* CAN FD Control Register */
CAN_0_FDCBT_tag FDCBT; /* CAN FD Bit Timing Register */
CAN_0_FDCRC_tag FDCRC; /* CAN FD CRC Register */
};

 

/* CAN 5.0.1 TAG ================================================= */

struct CAN_0_tag {
CAN_0_MCR_tag MCR; /* Module Configuration Register */
CAN_0_CTRL1_tag CTRL1; /* Control 1 register */
CAN_0_TIMER_tag TIMER; /* Free Running Timer */
uint8_t CAN_0_reserved0[4];
CAN_0_RXMGMASK_tag RXMGMASK; /* Rx Mailboxes Global Mask Register */
CAN_0_RX14MASK_tag RX14MASK; /* Rx 14 Mask register */
CAN_0_RX15MASK_tag RX15MASK; /* Rx 15 Mask register */
CAN_0_ECR_tag ECR; /* Error Counter */
CAN_0_ESR1_tag ESR1; /* Error and Status 1 register */
CAN_0_IMASK2_tag IMASK2; /* Interrupt Masks 2 register */
CAN_0_IMASK1_tag IMASK1; /* Interrupt Masks 1 register */
CAN_0_IFLAG2_tag IFLAG2; /* Interrupt Flags 2 register */
CAN_0_IFLAG1_tag IFLAG1; /* Interrupt Flags 1 register */
CAN_0_CTRL2_tag CTRL2; /* Control 2 register */
CAN_0_ESR2_tag ESR2; /* Error and Status 2 register */
uint8_t CAN_0_reserved1[8];
CAN_0_CRCR_tag CRCR; /* CRC Register */
CAN_0_RXFGMASK_tag RXFGMASK; /* Rx FIFO Global Mask register */
CAN_0_RXFIR_tag RXFIR; /* Rx FIFO Information Register */
CAN_0_CBT_tag CBT; /* CAN Bit Timing Register */
uint8_t CAN_0_reserved2[44];
CAN_0_RAMn_tag RAMn[384]; /* Embedded RAM */
uint8_t CAN_0_reserved3[512];
CAN_0_RXIMR_tag RXIMR[96]; /* Rx Individual Mask Registers */
uint8_t CAN_0_reserved4[256];
CAN_0_CTRL1_PN_tag CTRL1_PN; /* Pretended Networking Control 1 Register */
CAN_0_CTRL2_PN_tag CTRL2_PN; /* Pretended Networking Control 2 Register */
CAN_0_WU_MTC_tag WU_MTC; /* Pretended Networking Wake Up Match Register */
CAN_0_FLT_ID1_tag FLT_ID1; /* Pretended Networking ID Filter 1 Register */
CAN_0_FLT_DLC_tag FLT_DLC; /* Pretended Networking DLC Filter Register */
CAN_0_PL1_LO_tag PL1_LO; /* Pretended Networking Payload Low Filter 1 Register */
CAN_0_PL1_HI_tag PL1_HI; /* Pretended Networking Payload High Filter 1 Register */
CAN_0_FLT_ID2_IDMASK_tag FLT_ID2_IDMASK; /* Pretended Networking ID Filter 2 Register / ID Mask Register */
CAN_0_PL2_PLMASK_LO_tag PL2_PLMASK_LO; /* Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register */
CAN_0_PL2_PLMASK_HI_tag PL2_PLMASK_HI; /* Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register */
uint8_t CAN_0_reserved5[24];
CAN_0_WMB_tag WMB[4];
uint8_t CAN_0_reserved6[128];
CAN_0_FDCTRL_tag FDCTRL; /* CAN FD Control Register */
CAN_0_FDCBT_tag FDCBT; /* CAN FD Bit Timing Register */
CAN_0_FDCRC_tag FDCRC; /* CAN FD CRC Register */
};

 

P.S. I also noticed that the CSL flag is missing in revision 4.0.0. I went ahead and added it.

 

typedef union STM_CR_union_tag { /* STM Control Register */
vuint32_t R;
struct {
vuint32_t :16;
vuint32_t CPS:8; /* Counter Prescaler. */  /* <-- Missing in Revision 4.0.0 */
vuint32_t :3;
vuint32_t CSL:1; /* Clock Select. */
vuint32_t :2;
vuint32_t FRZ:1; /* Freeze. */
vuint32_t TEN:1; /* Timer counter Enabled. */
} B;
} STM_CR_tag;

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