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Adjust the DDR refresh interval

Question asked by ivan zhang on Mar 15, 2018
Latest reply on Mar 18, 2018 by ufedor

Can I adjust the register DDR_SDRAM_INTERVAL of P2020 after the MEM_EN bit of the register DDR_SDRAM_CFG has been setted ?

If it can't be realized, how can I adjust the refresh interval when the DDR controller is working ?