Ethernet Configuration on custom LS1046A board is not working.

[brunosauze]

We have designed a custom board based on LS1046A. On this board, Ethernet links are provided by a Quad PHY (Marvell) connected to the LS1046A through QSGMII.

When booting the board with u-boot, we are only able to access to one of the four internal MDIO interfaces (DTSEC6) while we expected to be able to access to the internal MDIO associated to the four DTSEC used in SGMII configuration (DTSEC1, DTSEC5, DTSEC6 and DTSEC10).

Our u-boot is derived from the u-boot used on eval board. For Ethernet configuration we have only modified eth.c to configure QSGMII and register MDIO bus (Clause 22 MDIO). 

Do you have any idea about what could prevent us from accessing MDIO registers of other DTSEC ?

On the working DTSEC we  have check the configuration on the PHY and on the DTSEC side (using MDIO interfaces):

  - The link is up,

  - Autonegotiation is successfull (100Base Tx FD)

  - Bit 14 in register 5 of the PHY is set (meaning DTSEC has acknowledged completion of autonegotiation).

 However ping towards external device is not working. We cannot even see the ARP frame on wireshark.

Is there any additional configuration we should do to have our Ethernet link working ?

How can we be sure that the ping command is sent to the PHY by the FMAN ?

Thanks 

Attached is the uboot log.

Original Attachment has been moved to: uboot.log.zip

[bpe]

There is too much confusion in this post, sorry. The only command appears in
the attached console log, if your PHY follows the standard MDIO registers
specification, displays the AN response of the far end to your PHY.
This register has nothing to do with any acknowledgement from LS1046 mEMAC.
If the problem is with the link between your Marvell PHY and the far
end, consult at it's manufacturer and documentation for troubleshooting.
Note that LS1046A Ethernet controller, mEMAC, does not acknowledge anything
to either the local or far end PHY because autonegotiation is not it's
function by MAC definition in IEEE802.3. Note also that all communication
to externally connected PHYs is done over a dedicated MDIO interfaces at
offsets 0x1AF_C000 for Clause 22 PHYs and 0x1AF_D000 for Clause 45 PHYs.
You do not have to alter anything in u-Boot except for the external PHY
addresses to control your PHYs over those interfaces.

Management ports that appear in each mEMAC address space are not visible
outside and are used to control on-chip PCS entities which are parts
of SerDes(not mEMAC!). Refer to LS1046ARM, Section 30.7 for the addressing scheme
details. The links between the on-chip PCS and the local PHY autonegotiate
separately and shall be distinguished from the far end links. These
links are initialized in dtsec_configure_serdes() defined in
drivers/net/fm/eth.c. The interface type is autodetected in
drivers/net/fm/ls1046.c so you don't have to alter anything for QSGMII.

As of the communication at FMan level, u-Boot initializes FMan in
independent mode, you can check whether or not your buffers have been
handled by reading BD status. Refer to LS1046DPAARM, Section 5.12.15.5.5
You can also read mEMAC statistics to see if anything has been
exchanged over the interace. Details can be found in LS1046ARM,
Section 6.4.3.2.

Have a great day,
Platon

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------