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i.MX6ULL How can is use input clocks CLK1, CLK2 to bypass the audio PLL generator?

Question asked by Gordon Rankin on Jun 29, 2017
Latest reply on Jun 30, 2017 by Gordon Rankin



I see in figure 10-3 of the Hardware Reference manual CLK1, CLK2 input into the clock block multiplexer section as well as the main 24MHZ oscillator. I see that there are pins CLK1_N/CLK1_P differential inputs for CLK1, but I cannot seem to find any reference to input CLK2 in the IO ALT#. There is a bunch of references to the CLK1/CLK2 outputs, just not the input CLK2.


I want to feed known audio Master Clocks into CLK2 single ended, bypass the audio pll and use this clock to derive the I2S and possibly SPDIF output feeds.