Hello,
Yes the capacitors are replaced with 0R resistors.
The issue is that the initialization process fails before accessing the RESET GPIO pins.
The function that fails is:
static void pci_imx_phy_pll_locked(struct imx6_pcie *imx6_pcie){
u32 val;
int count = 20000;
while (count--) {
regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
if (val & BIT(31))
break;
udelay(10);
if (count == 0)
pr_info("pcie phy pll can't be locked.\n");
}
}
We inspected the voltage on pins AA9, AA10, AA11, AA12 it seems to be ok.
The problem is very consistent on part of the boards:
- if one board is working it is 100% working, tested in 100 power ups
- If it fails then it fails, until the imx6_pcie->pcie_phy_regulator is not set to a higher level in this section:
static void imx6_pcie_init_phy(struct pcie_port *pp){
int ret;
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
if (is_imx7d_pcie(imx6_pcie)) {
/* Enable PCIe PHY 1P0D */
regulator_set_voltage(imx6_pcie->pcie_phy_regulator,1000000, 1000000);
ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
if (ret)
dev_err(pp->dev, "failed to enable pcie regulator.\n");
/* pcie phy ref clock select; 1? internal pll : external osc */
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,BIT(5), imx6_pcie->phy_refclk ? BIT(5) : 0);
/* get pcie phy out of reset to get correct clock rate */
regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), 0);
regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0);
regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(6), 0);
...
If the bold value is changed to 1100000 than all boards are working. But 1.1V is out of spec...
