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PCIe link doesn't come up with XIO2001 PCI bridge on iMX6Q custom board

Question asked by Roberto Fichera on Feb 3, 2016
Latest reply on Mar 15, 2016 by Roberto Fichera

Hi All,

 

I'm trying to get a custom board, based on iMX6Q SoC, to bring up the PCIe link connected to a TI XIO2001 PCIe-to-PCI bridge.

I've apply some changes to a uboot v2014.04 so that the give XIO2001 is properly reset, the relevant code is the following:

 

static iomux_v3_cfg_t const pcie_pads[] = {

         MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* WAKE */

         MX6_PAD_GPIO_9__GPIO1_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIE_PWR_EN */

         MX6_PAD_GPIO_16__GPIO7_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* GRST# */

         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PERST# */

};

 

#define PCIE_XIO2001_GRST IMX_GPIO_NR(7, 11)

#define CONFIG_PCIE_IMX_PERST_GPIO    IMX_GPIO_NR(7, 12)

#define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 9)

 

static void setup_iomux_pcie(void)

{

         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

}

 

int imx6_pcie_toggle_power(void)

{

#ifdef CONFIG_PCIE_IMX_POWER_GPIO

         /*

          * TI XIO2001 Power Up procedure:

          *

          * 1) Assert both GRST# and PERST# without power voltages

          */

     gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);

     gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);

     gpio_direction_output(PCIE_XIO2001_GRST, 0);

     mdelay(10);

 

         /*

          * 2) Apply 1.5V and 3.3V voltages ... but maybe only 3.3V ;)!

          */

     gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);

     mdelay(10);

 

         /*

          * 3) Deassert GRST#

          */

     gpio_set_value(PCIE_XIO2001_GRST, 1);

 

         /*

          * 4) After that we should apply a stable PCIe reference clock

          *    see drivers/pci/pcie_imx.c:imx6_pcie_deassert_core_reset()

          */

#endif

     return 0;

}

 

int imx6_pcie_toggle_reset(void)

{

#ifdef CONFIG_PCIE_IMX_PERST_GPIO

         /*

          * 5) To meet PCIe specific requirements, PERST# cannot be deasserted util minimum 100ms

          *    after apply power and 100-us after apply stable reference clock.

          */

     gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);

     mdelay(100);

     gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);

#else

     puts("WARNING: Make sure the PCIe #PERST line is connected!\n");

#endif

     return 0;

}

 

This will end up on this uboot boot status:

 

U-Boot 2014.04-imx_v2014.04_3.14.28_1.0.0_ga+g88123ea (Feb 03 2016 - 10:56:45)

 

CPU:   Freescale i.MX6Q rev1.5 at 792 MHz

CPU:   Temperature 37 C, calibration data: 0x5624d569

Reset cause: POR

Board: Janas iMX6Q (ID:e315c0641d0f31d4)

I2C:   ready

DRAM:  2 GiB

MMC:   FSL_SDHC: 0, FSL_SDHC: 1

MMC Device 3 not found

No MMC card found

Using default environment

 

 

Starting XIO2001 power up sequence ...

Enabling PCIe reference clock ...

Deasserting PCIe PERST# ...

Deasserting PCIe PERST# ...

phy link never came up

DEBUG_R0: 0x00354800, DEBUG_R1: 0x08200000

In:    serial

Out:   serial

Err:   serial

Found PFUZE100! deviceid=10,revid=21

Net:   FEC [PRIME]

Warning: failed to set MAC address

 

=> pci

Scanning PCI devices on bus 0

BusDevFun  VendorId   DeviceId   Device Class       Sub-Class

_____________________________________________________________

pci_bus_to_hose() failed

pci_bus_to_hose() failed

pci_bus_to_hose() failed

pci_bus_to_hose() failed

 

booting up a yocto kernel linux-fslc 4.1 I'm getting this:

 

[    0.537703] imx6q-pcie 1ffc000.pcie: phy link never came up

[    0.538363] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus 0000:00

[    0.538385] pci_bus 0000:00: root bus resource [io  0x1000-0xffff]

[    0.538403] pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]

[    0.538422] pci_bus 0000:00: root bus resource [bus 00-ff]

[    0.539694] PCI: bus0: Fast back to back transfers disabled

[    0.540036] PCI: bus1: Fast back to back transfers enabled

[    0.540206] pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]

[    0.540234] pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-0x0110ffff pref]

[    0.540254] pci 0000:00:00.0: PCI bridge to [bus 01]

[    0.541065] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt

 

root@voneus-janas-imx6q:~# lspci -vvv

00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01) (prog-if 00 [Normal decode])

        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+

        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

        Latency: 0, Cache Line Size: 64 bytes

        Interrupt: pin A routed to IRQ 290

        Region 0: Memory at 01000000 (32-bit, non-prefetchable) [size=1M]

        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0

        I/O behind bridge: 0000f000-00000fff

        Memory behind bridge: fff00000-000fffff

        Prefetchable memory behind bridge: fff00000-000fffff

        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-

        [virtual] Expansion ROM at 01100000 [disabled] [size=64K]

        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-

                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-

        Capabilities: [40] Power Management version 3

                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold+)

                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

        Capabilities: [50] MSI: Enable+ Count=1/1 Maskable+ 64bit+

                Address: 000000007d8b2000  Data: 0000

                Masking: 00000000  Pending: 00000000

        Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00

                DevCap: MaxPayload 128 bytes, PhantFunc 0

                        ExtTag- RBE+

                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+

                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-

                        MaxPayload 128 bytes, MaxReadReq 512 bytes

                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-

                LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <8us

                        ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp-

                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-

                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-

                RootCap: CRSVisible-

                RootSta: PME ReqID 0000, PMEStatus- PMEPending-

                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-

                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-

                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

                         Compliance De-emphasis: -6dB

                LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-

                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

        Capabilities: [100 v1] Advanced Error Reporting

                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-

                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-

                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+

                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

        Capabilities: [140 v1] Virtual Channel

                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1

                Arb:    Fixed- WRR32- WRR64- WRR128-

                Ctrl:   ArbSelect=Fixed

                Status: InProgress-

                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-

                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-

                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff

                        Status: NegoPending+ InProgress-

        Kernel driver in use: pcieport

 

Do you have any suggestion how to solve this?

 

Thanks in advance,

Roberto Fichera.

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