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P1020RDB-PD  TDM  tests and issues

Question asked by Naum Grutman on Feb 22, 2017
Latest reply on Aug 7, 2019 by Naum Grutman

In reference to the other thread:


TDM Driver Working in Internal Loopback mode During Validation 


The document within it  TDM Driver Working in Internal Loopback mode During Validation.pdf

described changes to the TDM driver more specifically 


#define TDM_CLK_DIV_VAL 0x85


#define TDM_CLK_DIV_VAL 0xC3 

within TDM_FSL.c


In that previous thread I have pointed out that first of all the TDM_LOOPBACK_TEST.c

algorithm had major issue and was actually failing 99% of the time...

That test was fixed up ( algorithmwise ) and it was shown to be PASSing for P1010RDB


Under further scrutiny my findings are:

Looking/reviewing again the test logs/results that you performed back in January using P1010 show that you were using

external clock... I would like to see you rerun your tests using internal clock on P1010 and see that you a get positive results...

Since you were using external clock the value of 0xC3 for TDM_CLK_DIV_VAL was not even used...


I am using P1020RDB-PD

the TDM_TEST.c  with the DTMF loopback and the freshly updated TDM_LOOPBACK_TEST.c are performing OK

as long as I am using the external clock...


if I use within TDM_FSL.c the following line

      dev_node = of_find_compatible_node( NULL, NULL, "fsl,P1020RDB-PD" );


to force P1020 to use internal clock... then both of above tests are FAILing...


I have tried these tests with each of the below values with not much luck...

#define TDM_CLK_DIV_VAL 0x85

#define TDM_CLK_DIV_VAL 0xC3 

Can you please run above tests on P1020RDB-PD using internal clock

and let me know what TDM_CLK_DIV_VAL should be set to...

and if there is any hope for these tests to PASS using INTERNAL CLOCK...



Naum Grutman