To anybody that has experience with P1020 and TDM,
I have a question a question about TDM on P1020
I have the TDM working just fine on within Linux and trying to make it it work within vxWorks
I have put together the the TDM driver for vxWorks based on the Linux driver within your SDK and also based on P1020 QorIQ Reference Manual Rev.6 page# 1519
I do steps 1 thru 4 and based on item number 5 I have to read the TSR and RSR and wait for those to get on...
but they never do... Could you shed some light on this subject...
and TDM GIR.
channel mask registers (TDM TCMAn ) as disabled.
bits.
the Tx data register(s) (must be completed before two Tx frame syncs arrive
after enabling).
before two Tx frame syncs arrive after enabling).
to enable channels.
depending on the configuration.
On Linux TDM TSR and TDM RSR do get set
====================================
F519A000: 00000001 0000E241 0000E041 007F0030 .......A...A...0
F519A010: 007F0030 007F0030 007F0030 007F0030 ...0...0...0...0
F519A020: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A030: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A040: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A050: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A060: 00000000 00000000 00000000 00000000 ................
F519A070: 00000000 00000000 00000000 00000000 ................
F519A080: 00000001 00000001 00000000 00000000 ................
F519A090: 00000000 00000000 00000000 00000000 ................
F519A0A0: 000001C0 000001C0 00000005 00000025 ...............%
On vxWorks instead of TSR and RSR I get 0x00000001 in Reserved fields marked in RED
==========================================================================
F3016000: 00000001 0000E241 0000E041 007F0030 .......A...A...0
F3016010: 007F0030 007F0030 007F0030 007F0030 ...0...0...0...0
F3016020: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016030: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016040: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016050: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016060: 00000000 00000000 00000000 00000000 ................
F3016070: 00000000 00000000 00000000 00000000 ................
F3016080: 00000001 00000001 00000000 00000000 ................
F3016090: 00000001 00000001 00000001 00000001 ................
F30160A0: 00000000 00000000 00000000 00000000 ................
Could you shed some light on this subject...
Thanks,
Naum
We do not have experience for VxWork using.
It looks like that debugging of your VxWorks driver is needed.
Have a great day,
Pavel Chubakov
Documentation for the P1020 does not have information about these reserved register.
Do you see incorrect behavior for your driver for the P1020 TDM?
Have a great day,
Pavel Chubakov
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Hello Pavel,
Let me clarify…
Within Linux environment P1020 TDM Regs at offset 0x16000 from CCSR
are mapped by Linux 0xFFE016000 -> 0xF519A000
Within Linux environment I do not have issues with TDM driver
as far as what I need the TDM driver to perform…
On Linux TDM TSR and TDM RSR do get set
====================================
F519A000: 00000001 0000E241 0000E041 007F0030 .......A...A...0
F519A010: 007F0030 007F0030 007F0030 007F0030 ...0...0...0...0
F519A020: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A030: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A040: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A050: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F519A060: 00000000 00000000 00000000 00000000 ................
F519A070: 00000000 00000000 00000000 00000000 ................
F519A080: 00000001 00000001 00000000 00000000 ................
F519A090: 00000000 00000000 00000000 00000000 ................
F519A0A0: 000001C0 000001C0 00000005 00000025 ...............%
When TCR gets set @ 0xF519A084 to 0x00000001 within microseconds
0xF519A0AC gets set in response to 0x00000025
and
0xF519A0A4 get set to 0x000001C0
When RCR gets set @ 0xF519A080 to 0x00000001 within microseconds
0xF519A0A8 gets set in response to 0x00000005
and
0xF519A0A0 get set to 0x000001C0
above line marked in green @ 0xF519A0A0 shows good results
Especially the fact that ReadOnly registers TDM TSR[TENS] and TDM RSR[RENS]
are set since this is what is needed for Step #5 on P1020 QorIQ Reference
Manual Rev.6 Chapter 19 page # 1519
Within vxWorks environment P1020 TDM Regs at offset 0x16000 from CCSR
are at 0xF3016000
I have adopted the TDM driver from Linux and rebuilt it for VxWorks environment
to do/accomplish the same data structures and tasks as they appear and performed
within Linux environment… 97 to 98% of the work is done…
The last girdle is that when TCR and RCR get set similar to the steps described above…
instead getting ReadOnly registers TDM TSR[TENS] and TDM RSR[RENS] set
I see that Reserved Area @ 0xF3016090 gets set to 0x00000001 as marked in RED
which should be an indication of something… but there is no documentation
how this should deciphered…TSR and RSR never get set and I cannot force them
since these are Read-Only fields... P1020 processor is in control...
P1020 processor sets the reserved fields to 0x00000001 which is indication of something
but what nobody knows since there is no documentation on these reserved fields...
On vxWorks instead of TSR and RSR I get 0x00000001 in Reserved fields marked in RED
==========================================================================
F3016000: 00000001 0000E241 0000E041 007F0030 .......A...A...0
F3016010: 007F0030 007F0030 007F0030 007F0030 ...0...0...0...0
F3016020: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016030: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016040: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016050: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................
F3016060: 00000000 00000000 00000000 00000000 ................
F3016070: 00000000 00000000 00000000 00000000 ................
F3016080: 00000001 00000001 00000000 00000000 ................
F3016090: 00000001 00000001 00000001 00000001 ................
F30160A0: 00000000 00000000 00000000 00000000 ................
Could you provide additional info or shed some light on this subject...
Thanks,
Naum