The ethernet isn't working on my EVK. It's detected at boot but fails to get an IP address from the router (which I've checked is working).
Configuring network interfaces... fec 20b4000.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=20b4000.ethernet:01, irq=-1)
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
No lease, forking to background
I read this thread (I.MX6UL EVK: Ethernet ports not working) and think that the required patch has been applied though I'm very new to Yocto! I rooted around until I found a file called mach-imx6ul.c then found that git said that it had a change not staged for commit (it wasn't me that patched it - how did I get someone else's unstaged commits ...)
chris:kernel-source$ git status
On branch imx_4.1.15_2.0.0_ga
Your branch is up-to-date with 'origin/imx_4.1.15_2.0.0_ga'.
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
no changes added to commit (use "git add" and/or "git commit -a")
chris:kernel-source$ git diff arch
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 034db69..25760bd 100644
@@ -50,10 +50,22 @@ static int ksz8081_phy_fixup(struct phy_device *dev)
-#define PHY_ID_KSZ8081 0x00221560
+ * i.MX6UL EVK board RevA, RevB, RevC all use KSZ8081
+ * Silicon revision 00, the PHY ID is 0x00221560, pass our
+ * test with the phy fixup.
+#define PHY_ID_KSZ8081_MNRN60 0x00221560
+ * i.MX6UL EVK board RevC1 board use KSZ8081
+ * Silicon revision 01, the PHY ID is 0x00221561.
+ * This silicon revision still need the phy fixup setting.
+#define PHY_ID_KSZ8081_MNRN61 0x00221561
static void __init imx6ul_enet_phy_init(void)
- phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup);
+ phy_register_fixup(PHY_ANY_ID, PHY_ID_KSZ8081_MNRN60, 0xffffffff, ksz8081_phy_fixup);
+ phy_register_fixup(PHY_ANY_ID, PHY_ID_KSZ8081_MNRN61, 0xffffffff, ksz8081_phy_fixup);
#define OCOTP_CFG3 0x440
Any clues would be gratefully received.