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Wrong LVDS-clock from i.MX6

Question asked by Steffen Doster on Oct 6, 2016
Latest reply on Oct 12, 2016 by Steffen Doster

Hi,

I'm running mad with that!

The i.MX6S on my custom board has only a display connected to LVDS0. I managed to get a working U-Boot and Linux 4.5 (mainline) environment.

But I still have a big problem with the display: the LVDS clock semm to be stuck at 72MHz (U-Boot) and 68MHz (Linux).

I already tried to change the timuings, but the clock dosn't ever change.

My configurations are derived from NXP's SabreSD-Board.

 

Heres my LDB-Entry from Devicetree:

Snippet
ldb: ldb@020e0008 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
        gpr = <&gpr>;
        clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
                   <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
                   <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
                   <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
                   <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
                   <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
        clock-names = "ldb_di0", "ldb_di1",
                        "di0_sel", "di1_sel",
                        "di2_sel",
                        "ldb_di0_div_3_5", "ldb_di1_div_3_5",
                        "ldb_di0_div_7", "ldb_di1_div_7",
                        "ldb_di0_div_sel", "ldb_di1_div_sel";
        status = "okay";
           lvds-channel@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
            fsl,data-mapping = "jeida";
            fsl,data-width = <24>;                    /* JEIDA only support 24bit */
            status = "okay";
               /*crtc = "ipu1-di0";*/
            /*fsl,data-mapping = "spwg";*/
            /*primary;*/
               display-timings {
                native-mode = <&timing0>;
                   /* Display Timings for TFT-Display DLC0700JMG */
                timing0: dlc0700jmg {
                    clock-frequency = <51200000>;
                    hactive = <1024>;
                    vactive = <600>;
                    hfront-porch = <16 160 216>;
                    hback-porch = <160>;
                    hsync-len = <1 70 140>;
                    hsync-active = <1>;
                    vfront-porch = <1 12 127>;
                    vback-porch = <23>;
                    vsync-len = <1 10 20>;
                    vsync-active = <1>;
                };
            };
               port@0 {
                reg = <0>;
                lvds0_mux_0: endpoint {
                    remote-endpoint = <&ipu1_di0_lvds0>;
                };
            };
               port@1 {
                reg = <1>;
                lvds0_mux_1: endpoint {
                    remote-endpoint = <&ipu1_di1_lvds0>;
                };
            };
        };
           /* LVDS-Channel 1 leads only to ICT-Pads and doesn't have any function. */
        lvds-channel@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
            crtc = "ipu1-di1";
            /*fsl,data-mapping = "jeida";*/
            fsl,data-mapping = "spwg";             fsl,data-width = <18>;
            status = "disabled";
               port@0 {
                reg = <0>;
                lvds1_mux_0: endpoint {
                    remote-endpoint = <&ipu1_di0_lvds1>;
                };
            };
               port@1 {
                reg = <1>;
                lvds1_mux_1: endpoint {
                    remote-endpoint = <&ipu1_di1_lvds1>;
                };
            };
        };
    }; 

And this is the timing in U-Boot:

struct display_info_t const displays[] = { {
    .bus     = -1,
    .addr     = 0,
    .pixfmt = IPU_PIX_FMT_LVDS666,
    .detect = NULL,
    .enable     = enable_lvds,
    .mode     = {
        .name = "DLC0700JBG",         // Typ. Clock Frequency = 51200000 Hz
        .refresh         = 60,
        .xres            = 1024,
        .yres            = 600,
        .pixclock        = 19531,   // = 10^12 / Clock Frequency
        .left_margin     = 160,
        .right_margin    = 160,
        .upper_margin    = 12,
        .lower_margin    = 23,
        .hsync_len       = 70,
        .vsync_len       = 10,
        .sync            = 0,
        .vmode           = FB_VMODE_NONINTERLACED
} }, followed by two unused timings

I already read, that there must be some misconfiguration about the wrong clock-parent or something like this

Outcomes