SPI DMA Clock spike

[nobodyKnows]

Hello,

the disable of the SPI causing a high and the enable causing a low on the spi clock line.

status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) {

...

     /* Disable SPI and then enable it, this is used to clear S register*/

    SPI_Enable(base, false);

    SPI_Enable(base, true);

...

}

My spi slave recognise this a one clock cycle. I think this is a bug in KSDK2.0.

Best regards

[xiangjun_rong]

Hi, Maximilian,

Regarding your question, can you tell me the part number you are using? as you know that there are two IP for SPI, one is used in Kl family, called SPI. Another is used in K family, called dspi. I suppose you use spi implemented for example in KL family.

This is the spi_enable() function:

static inline void SPI_Enable(I2C_Type *base, bool enable)

{

    if (enable)

    {

        base->C1 |= SPI_C1_SPE_MASK;

    }

    else

    {

        base->C1 &= ~SPI_C1_SPE_MASK;

    }

}

Setting the SPE bit in SPIx_C1 register "enables the SPI system and dedicates the SPI port pins to SPI system functions", it is possible that the SCK pin logic toggles after setting the SPE. But the CS pin is invalid when the SCK toggles after setting SPE bit, I do not think it can take effect on the SPI slave side.

In conclusion, from slave side, using a CS pin to enable slave spi instead of connecting the CS pin to GND in slave spi side, the CS pin is driven by master.

Hope it can help you.

BR

Xiangjun Rng

[nobodyKnows]

Hello,

I use a KL26. I have more than one device so I use several GPIOs for chip select. So this is really a Problem.

Best Regards,

Maximilian