strange question about MPC5744p DMA

[fyw]

i use dma transfer data from source --> destination,the program lists below.(See appendix for detailed code)

the question was caused by "dly = destination[10];   "

if there is no read of destination[], for example  use "dly = 100" instead of " dly = destination[10];   "    this program will work well

about dly = destination[X];  if X< 8  it seems that the first 8 data of   destination[] cannot be update by dma 

                                           if X>=8  it seems that the last 8 data of   destination[] cannot be update by dma  (PS: i am not try every index)

Thank you very much!

uint32_t source[16]={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};  
uint32_t destination[16]={0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0};

__attribute__ ((section(".text")))

int main(void)
{
uint32_t k,counter = 0;
uint32_t dly;

xcptn_xmpl ();              /* Configure and Enable Interrupts */

CLK_Init();
AIPS_0_Init();
DMA_0_Init();

for(;;)
{

       dly = destination[10];   /*this will cause strange phenomenon*/    

        for(k=0;k<dly;k++);

     //SoftTrig DMA
  DMA_0.TCD[0].CSR.B.START = 1u;
  while(DMA_0.TCD[0].CSR.B.DONE == 0u){};
  DMA_0.TCD[0].CSR.B.DONE = 0u;

        for(k=0;k<100000;k++);

        /*update the source data */
        for(k=0;k<16;k++)
        {
         source[k] = counter;
        }
        counter++;

}

return 0;

}

Original Attachment has been moved to: Example_Base.c.zip

[fyw · Accepted solution]

i find "disable dcache" before for(;;) can solve this problem

i wander why?  Is there any document about how to use cache?  Thank you very much!

void dcache_disable(void)
{
   register uint32_t val;

   E200CORE_SPR_GET(val,E200CORE_L1CSR0); /* L1CSR0 */
   val &= ~E200CORE_L1CSR0_CE;
   /* Memory Synchronize */
   E200CORE_SYNC();
   /* Instruction Synchronize */
   E200CORE_ISYNC();
   E200CORE_SPR_SET(E200CORE_L1CSR0,val);
   /* Instruction Synchronize */
   E200CORE_ISYNC();
}

[martin_kovar]

Hi,

using cache together with DMA causes this issue. Explanation is fairly simple. When some lines of RAM are cached, debugger reads this lines via core and it finds the data at first in cache. When there is cache hit (line of RAM is present in cache), data are read from cache memory instead of RAM memory. But DMA writes data directly to the RAM. This causes inconsistencies between data in RAM and cache. There are different data in RAM and different data in cache.

You should mark the part of RAM, which is used for DMA transfers as non-cacheable.

Please look at the following document, which could be helpful for you:

e200 Core Training relevant to MPC55xx and MPC56xx device family

Regards,

Martin

[fyw]

"You should mark the part of RAM, which is used for DMA transfers as non-cacheable."

------------- Is this configure SMPU_RGDn_WORD3.CI bit?  Thank you!

[martin_kovar]

Hi,

yes, this is the correct way.

Regards,

Martin

[fyw]

i read the smpu chapter and find that it mentioned the "master n"  i wonder what is the "master n"?  thank you very much!

which(below) is the "master n"?

[martin_kovar]

Hi,

the n means the logical master ID. For example master 2 is DMA, master 3 is FlexRay and so on, see table 7-12

Regards,

Martin