We have a B4860 on a custom board and due to HW issues with NOR we are trying to boot from SPI, however I am not having much luck and some bits don't quite add up.
I understand the PBI setting up the Complex memory to be SRAM and mapping it to 0xFFF8_0000 to 0xFFFF_FFFF (512KB)
I don't know what the following section does
#Configure alternate space
I presume the last PBI Flush PBL command copies the rest of the data (i.e. UBOOT) to SRAM
However when I compile UBOOT (using the SDK - I created the entry to add SPI build) the UBOOT image is 768 KB and the B4860_SPIFLASH.conf has SYS_TEXT_BASE set to 0xFFF4_0000 so outside of the SRAM area. If I try and change the SYS_TEXT_BASE to 0xFFF8_0000 the compile fails as everything has to move location as it doesn't fit.
So my question is how does this ever work? Am I missing something (I have no doubt I am)?
Would it work to setup both CPC memory to SRAM interlaced and then map in the area?
For some reason CW (10.5.1) doesn't contain the tcl and MEM files for debugging from SPI\CPC but will try and create them by looking at others.
Any help or indication/pointing in the right direction would be great