With the IMX6 configured as a PCIe endpoint, I try to setup BAR0 and BAR1 as 32 bit memory BARs. The problem is that if BAR0 is configured to be a 32 bit memory BAR it seems that whatever I set in the BAR1 mask register is ignored. This is what I do in the code:
|// setup BAR0 and its mask|
|// setup BAR1 and its mask|
When the RC enumerates the endpoint and writes 0xFFFFFFFF to each BAR and then reads them back, BAR0 returns 0xFFFF0000 as expected. But BAR1 returns 0x00000000. If I change BAR0 to be a 64 bit BAR (RegWrite(Registers32::PCIE_EP_BAR0, 0x4);) but change nothing else, then BAR1 seems to work and the RC sees it request 64K of memory as expected.
I'm using a PCIe bus analyzer to verify the config reads and writes so I know it's not an issue with the RC. These are the values actually going across the wire to and from the IMX6.
Can a freescale engineer look into this please? Both the datasheet and the linux example code do not enable BAR1 as a 32 bit BAR so I'm wondering if this has ever been tested or if there is a bug in the part itself. Thanks.