PWM dutycycle of 0% using SCTtimers?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by renskessener on Wed Feb 17 14:14:44 MST 2016
I want to make a PWM signal with a dutycycle from 0 – 100% in 64 steps.
(Actually I need 4 PWM’s but if one works I can make 4 work)
It must be possible to have 0% dutycycle.

I thought SCT timers would be the best choice.

I am new to LPC processors and I don’t understand (yet) all items in the user manual.
I use the LPC11U68 board as a vehicle to figure things out.
I used the example (in LPCopen) “ periph_SCT_PWM” as a guide.

Using STC1:
I set the MATCH0 and MATCHREL0 registers to 63 to represent PWM-cycle length.
I use MATCH1 and MATCHREL1 registers as the dutycycle register.
By changing the MATCHREL1 register to a new desired dutycycle, the MATCH1 register will follow the next cycle as I understand. It varies from 0 to 63.
EVENT[0] is used to signal a match for the PWM-cycle length and sets OUT0 to 1.
EVENT[1] is used to signal a match for the dutycycle and sets OUT0 to 0.
SCT_EVENT_0 and SCT_EVENT_1 bothe enable STATE0.
I think I do not need states.

It works, BUT at a dutycycle of 0, OUT0 still produces a pulse.
Probably because EVENT[0] take precedence or because, if MATCH1 == 0,  EVENT[1]  happens
At the first clockcycle.?????

Do I misunderstand the capabilities of the SCT-timers?
What do I do wrong?
Is there an example out there that makes a PWM that includes 0% dutycycle?

Thanks in advance