Content originally posted in LPCWare by gstraka on Tue Apr 12 19:32:57 MST 2016
Quote: renskessener
From gstraka:
Edit: Actually with the above solution, it's possible to get a 0% duty cycle but not a 100% duty cycle. It's basically reversing the problem, no?
Yes, I agree. It reverses the problem. It is either 0% but not 100% or 100% and not 0%.
I figured out how to do it by using centre aligned PWM and a bidirectional counter. That works perfect.
Later I found It is also described in AN11538 (SCTimer/PWM cookbook), chapter 20.
So, for me the problem is solved.
Thanks for the replies.
Maybe it's just me, but it seems like chapter 20 of AN11538 has some errors. For example:
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[*]It says "MATCH[1].L = 0 results in 0% duty cycle (signal OFF)". I agree with this one.
[*]It says "MATCH[1].L = MATCH[0].L - 1 results in 100% duty cycle (signal ON)." This seems wrong, wouldn't it result in a near-0% duty cycle? To get 100% MATCH[1].L would have to equal MATCH[0].L.
[*]It says "0 < MATCH[1].L < MATCH[0].L - 1 results a 1 to 99% duty cycle." This seems correct except that the example implementation has it backwards. MATCH[1].L = 1 should result in a near-100% duty cycle while MATCH[1].L = MATCH[0].L - 1 should result in a near-0% duty cycle.
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Am I off base here?