MII-MDIO clocking and control

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by aras on Tue Feb 26 09:15:58 MST 2013

The UM10503 43xx user manual indicates that the MDC clock is derived from the Ethernet block register interface clock CLK_M4_ETHERNET, and can be divided down by various ratios as indicated in the CR[4:0] field of MAC_MII_ADDR, address 0x4001 0010. I note that much of the example ENET driver code does not set this correctly which means that the clock runs completely out of spec (though it "works"). The description of "bit 5" (quoted below) is nonsensical and the division ratios a little random!

Q1) Is it the case that the only way to change the MDC frequency is thru these control bits and by adjusting the CPU clock?
Q2) Adjusting the CPU clk has some limitations ( in the usr manual) when increasing frequency. Is there further info on exactly the limitations, please? I.e. is this a PLL issue or a clock-tree issue?  So, is it always OK to switch CPU clk back and forth, say between PLL1 and IRC? This is an important consideration for us more in low power than MDIO function, of course.

Thanks, Richard.

The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.
When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.
See Table 547 for bit values.