SDRAM controller

[lpcware]

Content originally posted in LPCWare by PhilYoung on Thu Apr 05 10:49:12 MST 2012
Trying again, so apologires if this gets duplicated.
I'm having difficulty getting SDRAM to work with the M4 running at 200 MHz.
I modified the SDRAM example to get a 128 Mb 32 bit 4 bank SDRAM working reliably at 100 MHz, and extended the SDRAM tests to be much more exhaustive and over a larger area.
I also tested the SDRAM in both ROW_BANK_COLUMN and BANK_ROW_COLUMN configurations, both work perfectly with the CPU at 100 MHz and not at 200 MHz.

then Added the following code to set the EMC to operate at 100 MHz withh the CPU at 200 MHz using EMC_CLK_DIV.

   LPC_CCU1->CLK_M4_EMCDIV_CFG = 0x21; // enabled / divide by 2 for 100Mhz
   LPC_CREG->CREG6 = LPC_CREG->CREG6  | 0x10000; // set EMC_CLK_SEL

( the obvious thinh would be timing parameters, but I use 10ns for the clock period in both cases rather than the system reported CPU clock speed used in the example).

I find very strange behaviour, at 100MHZ the SDRAM is 100% reliable, but using exactly the same setup, only changing the CPU clock and using EMC_CLK_DIV the SDRAM starts to show a failure of about 0.1% write errors.

The write errors take 2 forms.
Sometimes a number of 4 word blocks simply don't get updated ( each location has a unique value and the value does not appear elswehere ).
At other times I get data duplication, always if I expect Y at location (X) and Z at location (X + 16) ( 4 words later ) I actually find Z at both locations.

This is very strange behaviour, I've seen similar behaviour years ago with SRAM, but the failure mechanism that caused duplicated writes there should be impossible in SDRAM.

Has anybody else tried using the SDRAM controller at half the CPU speed with the CPU at 200 MHz?.

has anybody got any suggestions ( I spent 2 days trawling through the SDRAM and LPC4350 manuals and cannot see anything wrong ).

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed Apr 18 15:59:42 MST 2012
a few points.
I have SDRAM working correctly now, and NXP have tested my setup on the Hitex boards soI know that the board works.

The memory controller buffers reads / writes so you can be fooled into thinking SDRAM is working when in fact all you are seeing is the contents of the buffer in the memory controller.

It is important to ensure correct alignment of the mode command written to the SDRAM, this must match the mode you configure the SDRAM controller in, i.e. Row Bank Column, or Bank Row Column which affects the alignment of the mode command.

Single stepping SDRAM setup can brreak thinks if you try single stepping the commands to the SDRAM with anything displayed in the debugger which access the SDRAM as this will cause a bus cycle which the SDRAM mis-interprets as the command.

The same problem can occur if you have the periodic update enabled in the debugger.

If you change the clock speed and use the example setup code you must do so before setting up the SDRAM controller as it uses the computed clock speed to compute the values written to the SDRAM controller.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by jimmcwin on Wed Apr 18 14:20:30 MST 2012
I have a LPC4350 Hitex board and I am having problem with sizing the external SDRAM chip. I am using sample codes provided from LPCWARE dated 1/25/2012. The code run from SRAM via ULINK2 debugger with simple scheme to check for memory content wrapping around. It seems like there is a timing and long  word issue. The code write a long and memory window show data valid only in word.

Has anyone got this board working with SDRAM correctly ?
Is the EMC_Sdram_Init funtion provided by LPCWARE buggy ?

Thank you,

Jim

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed Apr 18 07:55:41 MST 2012
It seems that with the SDRAM address buffers removed the device can operate correctly in both modes, so there is a slight DRAM timing difference when using EMC_CLK_DIV for the EMC clock.