Content originally posted in LPCWare by oliveryang on Tue Aug 19 00:38:19 MST 2014
Hi,
I was trying the LPCOpen example on Keil MCB4357 board but encountered an issue.
The examples I was running are "FreeRTOS Blinky" located in "\applications\lpc18xx_43xx\iar_ewarm_projects\keil_mcb_4357\dualcore\freertos_blinky" and "\applications\lpc18xx_43xx\iar_ewarm_projects\keil_mcb_4357\dualcore\freertos_blinky_m0." Both projects passed the build, and I could download the image into M4 core with no problem. When I tried to download the image into M0 core, it showed "execution failure in flash loader."
Does anyone have idea what did I miss here to run the example? Thanks for your help.
The log is attached below.
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Tue Aug 19, 2014 14:42:17: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac
Tue Aug 19, 2014 14:42:17: Skipping flash loading pass because there is no data in the designated range: 0x1A000000-0x1A7FFFFF.
Tue Aug 19, 2014 14:42:17: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac
Tue Aug 19, 2014 14:42:18: JLINK command: ProjectFile = D:\nxp_workplace\applications\lpc18xx_43xx\iar_ewarm_projects\keil_mcb_4357\dualcore\freertos_blinky_m0\settings\freertos_blinky_m0_iflash_keil_mcb_4357.jlink, return = 0
Tue Aug 19, 2014 14:42:18: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\NXP\LPC4350_DebugCortexM0.JLinkScript, return = 0
Tue Aug 19, 2014 14:42:18: Device "LPC4357_M0" selected (0 KB flash, 0 KB RAM).
Tue Aug 19, 2014 14:42:18: DLL version: V4.82
Tue Aug 19, 2014 14:42:18: Firmware: J-Link V9 compiled Mar 10 2014 19:02:08
Tue Aug 19, 2014 14:42:18: JTAG speed is initially set to: 32 kHz
Tue Aug 19, 2014 14:42:18: TotalIRLen = 8, IRPrint = 0x0011
Tue Aug 19, 2014 14:42:19: TotalIRLen = 8, IRPrint = 0x0011
Tue Aug 19, 2014 14:42:19: Found Cortex-M0 r0p0, Little endian.
Tue Aug 19, 2014 14:42:19: FPUnit: 2 code (BP) slots and 0 literal slots
Tue Aug 19, 2014 14:42:19: LPC43xx Cortex-M0 (reset): Performing core reset for Cortex-M0 co-processor. No other reset types available for this core.
Tue Aug 19, 2014 14:42:19: Warning: T-bit of XPSR is 0 but should be 1. Changed to 1.
Tue Aug 19, 2014 14:42:19: Warning: T-bit of XPSR is 0 but should be 1. Changed to 1.
Tue Aug 19, 2014 14:42:19: J-Link script: Performing reset sequence
Tue Aug 19, 2014 14:42:19: Warning: T-bit of XPSR is 0 but should be 1. Changed to 1.
Tue Aug 19, 2014 14:42:19: Hardware reset with strategy 0 was performed
Tue Aug 19, 2014 14:42:19: Initial reset was performed
Tue Aug 19, 2014 14:42:19: Found 2 JTAG devices, Total IRLen = 8:
Tue Aug 19, 2014 14:42:19: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Aug 19, 2014 14:42:19: #1 Id: 0x0BA01477, IRLen: 4, IRPrint: 0x1 CoreSight SW-DP
Tue Aug 19, 2014 14:42:19: ------- Prepare for flashloader -------
Tue Aug 19, 2014 14:42:20: 1504 bytes downloaded and verified (15.79 Kbytes/sec)
Tue Aug 19, 2014 14:42:20: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\NXP\FlashNXPLPC18xx_RAM40K.out
Tue Aug 19, 2014 14:42:20: Target reset
Tue Aug 19, 2014 14:42:20: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac
Tue Aug 19, 2014 14:42:20: Execution failure in flash loader.