UART TX interrupt: should I put at least one byte in the TX FIFO?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by giusloq on Thu Feb 12 04:16:12 MST 2015
I'm trying to use the UART peripheral in LPC4350 MCU in interrupt mode, but I failed.

With other MCUs (AVR and SAMD20 from Atmel), I usually enable the TX register empty interrupt (IER->THREIE) as soon as I need to send some bytes, and before pushing any byte in the TX register/FIFO. The interrupt is immediately fired up, because the TX register/FIFO is really empty.

The behaviour of UART peripheral on LPC4350 MCU seems different. The THRE interrupt isn't immediately fired as soon as setting IER->THREIE bit, but I need to push at least one byte in TX FIFO to have the interrupt. It seems the THRE interrupt is "edge-triggered" (triggered when the TX FIFO switch from non empty to empty state) and not "level-triggered" (triggered when the TX FIFO is currently empty, indipendent from a previous state).
I'd like to push the first byte inside interrupt handler, so I need the interrupt even if the TX FIFO is empty.

The uart example in LPCopen really starts pushing bytes into TX FIFO, but if I change the code to avoid pushing the first byte, the interrupt isn't fired.

It seems an odd behaviour to me, so I'm thinking I made some mistake. Could someone confirm the odd behaviour is the real one, or did I make some mistake?