;-----------------------------------------------------------------------!
; Sio IrqHandler!
;-----------------------------------------------------------------------!
fn UioIrq0
movsr0, 0; channel 0
b.nUioIrqHandler;
fe UioIrq0
etc.
;-----------------------------------------------------------------------!
; Sio IrqHandler!
;-----------------------------------------------------------------------!
fn UioIrqHandler
adrr3, sioTbl; get channel specific details
addsr3, r3, r0, lsl 5; tbl+channel*32
ldrr2, [r3, 28]; get ucb
ldrr3, [r3, 0]; get peripheral base addr
movsr12, 0; initially, turn off the THRE mask
;---------------------------------------;
0:ldrr0, [r3, uStatus]; check status flags
bicsr0, r12; but mask unwanted bits
ldrr1, [r3, uIntID]; read interrupt status register
tstr0, (1<<0); rxRdy
bne20f; yup
tstr0, (1<<5); txRdy
beq9f; nope -- ignore line status
;---------------------------------------;
; transmit next character;
;---------------------------------------;
10:ldrr1, [r2, uTxHead]; head offset
ldrr0, [r2, uTxTail]; tail offset
cmpr0, r1; any more to xmit?
bne12f; yup
;---------------------------------------;
11:ldrr0, [r3, uIrqEnable]; no more chars
bicsr0, (1<<1); disable TxRdy
strr0, [r3, uIrqEnable];
movsr12, (1<<5); and set mask also
b0b; see if more to do
;---------------------------------------;
12:ldrr0, [r2, uTxBase]; buffer base addr
ldrbr0, [r0, r1]; get next char
strr0, [r3, uTxChar]; xmit
addsr1, 1; bump
movwr0, txBfSz-1; with wrap
andsr1, r0;
strr1, [r2, uTxHead]; update head
b0b; see if more to do
;---------------------------------------;
; character received;
;---------------------------------------;
20:ldrr1, [r2, uRxBase]; buffer base addr
ldrr0, [r2, uRxTail]; tail offset
addsr1, r0; now a pointer
ldrr0, [r3, uRxChar]; get the character
strbr0, [r1]; stash
ldrr0, [r2, uRxTail]; tail offset
addsr0, 1; bump
movwr1, rxBfSz-1; wrap factor
andsr0, r1; with wrap
strr0, [r2, uRxTail]; update tail
b0b; see if more to do
;---------------------------------------;
9:bxlr; return
fe UioIrqHandler
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