lpcware

LPC4370 High Speed ADC initial delay.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by mshrestha789 on Tue Nov 03 10:56:12 MST 2015
Hello friends,

Recently I have been working on High speed ADC of the LPC4370 microcontroller. I need to detect the threshold and then capture the data, I managed to do that however, many times ADC misses certain data at the beginning. I attached here the screeshot of the captured data and part of ADC code. This behavior very random. Please help me regarding this.


void adc_init(void){
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2); // USB clock 480 MHz -> CLKIN_IDIVA = 480/2=240
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 3);  // CLCIN_IDIVB = CLKIN_IDIVB = 240/3 = 80
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false);


Chip_Clock_EnableOpts(CLK_ADCHS, true, true, 1);
Chip_HSADC_Init(LPC_ADCHS_CMSIS);


Chip_HSADC_SetupFIFO(LPC_ADCHS_CMSIS, 8, true);
Chip_HSADC_ConfigureTrigger(LPC_ADCHS_CMSIS, HSADC_CONFIG_TRIGGER_SW, HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC, HSADC_CHANNEL_ID_EN_ADD, 0x90);


Chip_HSADC_SetACDCBias(LPC_ADCHS_CMSIS, 0, HSADC_CHANNEL_NODCBIAS, HSADC_CHANNEL_NODCBIAS);

Chip_HSADC_SetThrLowValue(LPC_ADCHS_CMSIS, 0, 10);
Chip_HSADC_SetThrHighValue(LPC_ADCHS_CMSIS, 0, 3000);

Chip_HSADC_SetPowerSpeed(LPC_ADCHS_CMSIS, false);
Chip_HSADC_EnablePower(LPC_ADCHS_CMSIS);

Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 0, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 1, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 2, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 3, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 4, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 5, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 6, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 0, 7, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_SWAP | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 0, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 1, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 2, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 3, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 4, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 5, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 6, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_BRANCH_NEXT | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS_CMSIS, 1, 7, (HSADC_DESC_CH(0) | HSADC_DESC_THRESH_A | HSADC_DESC_INT | HSADC_DESC_BRANCH_SWAP | HSADC_DESC_MATCH(HSADC_DESCRIPTOR_TIME) | HSADC_DESC_RESET_TIMER));

Chip_HSADC_UpdateDescTable(LPC_ADCHS_CMSIS, 0);
Chip_HSADC_UpdateDescTable(LPC_ADCHS_CMSIS, 1);
}

static void vadc_control_task(void *pvParameters){
while (1) {
if(xSemaphoreTake(g_adc_trigger, 10)== pdTRUE){ //wait for trigger
Chip_HSADC_SetActiveDescriptor(LPC_ADCHS_CMSIS, 0, 0); // set active descriptor
Chip_HSADC_SWTrigger(LPC_ADCHS_CMSIS); //software trigger
while((Chip_HSADC_GetLastSample(LPC_ADCHS_CMSIS, 0) & HSADC_LS_RANGE_ABOVE) != HSADC_LS_RANGE_ABOVE); //wait for threshold
Chip_HSADC_FlushFIFO(LPC_ADCHS_CMSIS);
LPC_GPDMA->C0CONFIG  |=  (0x1); //initialize DMA transfer
while(1){
if(LPC_GPDMA->INTTCSTAT & (((1UL << 0) & 0xFF))){
break;
}
}

}
}

Attachments

Outcomes