Content originally posted in LPCWare by cosborne2000 on Tue Jun 17 08:44:28 MST 2014
I'm new to the ARM Cortex and writing a driver for FTDI's FT1248 bus.
The potential problem is that the FT1248 bus uses a MIOSIO line so the SPI interface isn't standard. Using the hardware SPI (no bit-banging), I'm hoping to accommodate the direction change by using the switch matrix to move the MOSI line "out of the way" during the master read portion (LPC15 is the master).
My strategy is:
1- switch matrix places MOSI on MIOSIO pin
2- LPC15 writes data to FT1248 bus
3- switch matrix places MISO on MIOSIO pin and moves MOSI to another pin (maybe 255?)
4- LPC15 reads data from FT1248 bus.
note: read only transactions won't need this pin movement.
A few questions I couldn't find in the documentation:
How many clock cycles does the matrix use to complete the pin connection?
Can I move peripheral pins while the peripheral is enabled?
Does moving a function to position 255 (default) basically disconnect the function?
