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MPC5643L_some details about CTU FIFO and DMA

Question asked by na yan on May 5, 2016
Latest reply on May 9, 2016 by Peter Vlna

About CTU FIFO

 

Q1: I want to use CTU trigger send a command to ADC, then use FIFO 0 overflow event trigger a DMA transfer. I feel unsure about the FIFO 0 threthold value. For example:

IF FIFO 0 threthold equals 4, how many ATD results when FIFO 0 contains will cause a DMA transfer, 4 or 5 ?

 

 

Q2: I cann’t quite understand the FIFO control register,for example: FIFO 0 overflow interrupt enable bit .

CTU_FIFO0.png

From the corresponding codes of MPC5643L technical support (PWM triggered measurement concept) written by Peter Vina and AN4797 by Yves Briant ,we get know that they both use FIFO 0 overflow event trigger a DMA transfer. What’s the relationship between the event and FIFO 0 overflow interrupt enable bit which they both set?

 

Following code is from the technical support by Peter Vina.

 

CTU.TH1.B.THRESHOLD0 = 0xE;   /* FIFO 0 Threshold. Maximum value of 15, as the threshold value must be less than the

                       number of FIFO 0 entries. */

CTU.FCR.B.FIFO_OVERFLOW_EN0 = 1;  /* FIFO 0 threshold Overflow interrupt enable - read FIFO 0 in this nterrupt */

 

I think we only need to configure the corresponding DMA enable bit for FIFO 0 bit and DMA channel source, isn’t it right? Why we need to configure   FIFO 0 overflow interrupt enable bit ?

Such as   CTU.FDCR.R  = 0x1; // Enable DMA for FIFO0

                 DMAMUX.CHCONFIG[5].B.SOURCE = 8;   // CTU FIFO0 threshold

 

Thanks very much!

Yanna

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