MMA51xx & MMA52xx Accelerometers

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MMA51xx & MMA52xx Accelerometers

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davebarnett
Contributor I

Are MMA51xx & MMA52xx accelerometers susceptible to single event upsets? If so, are there any on-board error detection or error correction capabilities?

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david_diaz
NXP Employee
NXP Employee

Hello Dave,

By single event upset what you exactly mean?

Can you elaborate on this a little bit more? May be like what happens to sensor after a shock event?

Have a great day.

David

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davebarnett
Contributor I

Single event upsets (SEUs) are radiation-induced errors in microelectronic devices caused by ionizing particles, also commonly referred to as a bit-flip. With the MMA accelerometers, a concern would be if a single "bit-flip" could significantly affect the operation of the sensor. For example, could a bit flip internal to the sensor cause a +/- 480 g device to think is was a +/- 120 g device, resulting in a 120 g acceleration being reported as full scale, which would inadvertently be interpreted as a 480 g acceleration by the processor that is receiving the data from what it thinks is a +/- 480 g device. Some device types are less susceptible to SEUs (e.g. anti-fuse FPGA). I cannot find any information on the MMA51/52 devices that describes their immunity to SEUs.

Best regards,

Dave

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david_diaz
NXP Employee
NXP Employee

Hello Dave,

I apologize for the delay.

Unfortunately, SEU doesn’t apply to MMA5xxx because it was designed using 250nm process and SEU applies only to processes with much smaller geometries (< ~ 180 nm).

In addition, MMA5xxx has 3-bit CRC which is continuously run on the fuse mirror registers.  The CRC is guaranteed to detect all single bit errors. The CRC has a hamming distance of 3 so it will also detect up to 3-bit burst (contiguous) errors. 

I hope this information will be useful for you.

If I misunderstood your question, feel free to let me know.  I will be glad to help.

Have a great day.

David Diaz.

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