When a loss of PLL/XOSC clock signal occurs,how long will the PLL still work at least?
And if a long or short reset is selected,where will the source of failure be store?
If you choose reset long/short reaction, then after reset you will see MC_RGM_FES[F_FCCU_HARD/F_FCCU_SOFT] flag set and FCCU module will be in FAULT status.
FCCU hard reaction request <=> Long Functional reset
FCCU soft reaction request <=> Short Functional reset
As it is being reported by FCCU module that is clocked by internal RC oscillator, it’ll take several IRC clocks.
For the event when a clock failure occurs,if the FCCU is programmed to generate an interrupt,and how can I switch the system clock to IRCOSC?
The best is to trigger SAFE mode in mode entry module.
OK,but I want to know whether it has enough time to trigger SAFE mode when the system clock failure(Loss of PLL/XOSC clock),and what is the source of system clock before it trigger SAFE mode?
Chapter 13.8.1 says:
“In the case of the interrupt, only the unpredictable free running clock is still provided by the PLL. There is no automatic system clock switch in this case, and the user is required to program the switch through the Mode Entry module (MC_ME). Therefore, it is strongly recommended that the interrupt reaction to a PLL loss of lock is not selected when the PLL is used as the source of the system clock.”
It means that in case PLL unlock occurs, PLL still clocks the core (by unstable clock) into the interrupt where application would trigger SAFE mode. It is however not recommended - FCCU should be set to trigger reset and after reset application should investigate its reason and go to SAFE mode if needed.
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