I have a data cache coherency issue during implementing UART by DMA. When I disabled the data cache, the issue was never occurred on rx buffer which is in SRAM. But without data cache, total MCU performance was poor than before, so I wanted to set a cache inhibit range by SMPU.
/* Region 1: Shared data 16 bytes long inside SRAM, cache inhibited */
SMPU_1.RGD.WORD0.R = (uint32_t)&UART_RX_buffer; /* Reg start addr*/
SMPU_1.RGD.WORD1.R = (uint32_t)&UART_RX_buffer; /*Region end */
SMPU_1.RGD.WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */
SMPU_1.RGD.WORD3.R = 0x00000002; /* Region cacheable: Cache Inhibit=2*/
SMPU_1.RGD.WORD4.R = 0x00000000; /* PID not included in region eval. */
SMPU_1.RGD.WORD5.R = 0x00000001; /* Region is valid without lock */
I found this code from AN4830.
However, the cache coherent issue is still occurred even I used SMPU. So the question is, is there anything that I missed?
According to AN4856, I found that user must place the specific section into the section map of the memory region. If is this step should be done to resolve the cache coherent issue?