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MPC5748G : question about inhibiting D-cache by SMPU

Question asked by Neo Jung Employee on Mar 4, 2016
Latest reply on Mar 7, 2016 by Lukas Zadrapa

Hello Sir,

 

I have a data cache coherency issue during implementing UART by DMA. When I disabled the data cache, the issue was never occurred on rx buffer which is in SRAM. But without data cache, total MCU performance was poor than before, so I wanted to set a cache inhibit range by SMPU.

 

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    /* Region 1:  Shared data 16 bytes long inside SRAM, cache inhibited */

    SMPU_1.RGD[1].WORD0.R = (uint32_t)&UART_RX_buffer[0]; /* Reg start addr*/

    SMPU_1.RGD[1].WORD1.R = (uint32_t)&UART_RX_buffer[13]; /*Region end */

    SMPU_1.RGD[1].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[1].WORD3.R = 0x00000002;  /* Region cacheable: Cache Inhibit=2*/

    SMPU_1.RGD[1].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[1].WORD5.R = 0x00000001;  /* Region is valid without lock */

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I found this code from AN4830.

 

However, the cache coherent issue is still occurred even I used SMPU. So the question is, is there anything that I missed?

According to AN4856, I found that user must place the specific section into the section map of the memory region. If is this step should be done to resolve the cache coherent issue?

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