MPC5748G : question about inhibiting D-cache by SMPU

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

MPC5748G : question about inhibiting D-cache by SMPU

Jump to solution
1,144 Views
neojung
NXP Employee
NXP Employee

Hello Sir,

 

I have a data cache coherency issue during implementing UART by DMA. When I disabled the data cache, the issue was never occurred on rx buffer which is in SRAM. But without data cache, total MCU performance was poor than before, so I wanted to set a cache inhibit range by SMPU.

 

=============================

    /* Region 1:  Shared data 16 bytes long inside SRAM, cache inhibited */

    SMPU_1.RGD[1].WORD0.R = (uint32_t)&UART_RX_buffer[0]; /* Reg start addr*/

    SMPU_1.RGD[1].WORD1.R = (uint32_t)&UART_RX_buffer[13]; /*Region end */

    SMPU_1.RGD[1].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[1].WORD3.R = 0x00000002;  /* Region cacheable: Cache Inhibit=2*/

    SMPU_1.RGD[1].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[1].WORD5.R = 0x00000001;  /* Region is valid without lock */

=============================

I found this code from AN4830.

 

However, the cache coherent issue is still occurred even I used SMPU. So the question is, is there anything that I missed?

According to AN4856, I found that user must place the specific section into the section map of the memory region. If is this step should be done to resolve the cache coherent issue?

Labels (1)
0 Kudos
1 Solution
658 Views
neojung
NXP Employee
NXP Employee

Hello Lukas,

Yes, the UART_RX_buffer is aligned to 16 bytes but after I divided the region like below, the issue was fixed and maybe the root cause is SMPU doesn't support duplicated region.

Thank you for your help!

Best regards,

Neo

    /* Region 0:  All internal SRAM of 768KB */

    SMPU_1.RGD[0].WORD0.R = 0x40000000;  /* Region start addr- start of SRAM */

    SMPU_1.RGD[0].WORD1.R = 0x400006CF;  /* Region end addr- end of SRAM  */

    SMPU_1.RGD[0].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[0].WORD3.R = 0x00000000;  /* Region cacheable: Cache Inhibit=0*/

    SMPU_1.RGD[0].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[0].WORD5.R = 0x00000001;  /* Region is valid without lock */

    /* Region 1:  Shared data 16 bytes long inside SRAM, cache inhibited */

    SMPU_1.RGD[1].WORD0.R = 0x400006D0; /* Reg start addr*/

    SMPU_1.RGD[1].WORD1.R = 0x400006EF; /*Region end */

    SMPU_1.RGD[1].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[1].WORD3.R = 0x00000002;  /* Region cacheable: Cache Inhibit=2*/

    SMPU_1.RGD[1].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[1].WORD5.R = 0x00000001;  /* Region is valid without lock */

    SMPU_1.RGD[2].WORD0.R = 0x400006F0;  /* Region start addr- start of SRAM */

    SMPU_1.RGD[2].WORD1.R = 0x400BFFFF;  /* Region end addr- end of SRAM  */

    SMPU_1.RGD[2].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[2].WORD3.R = 0x00000000;  /* Region cacheable: Cache Inhibit=0*/

    SMPU_1.RGD[2].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[2].WORD5.R = 0x00000001;  /* Region is valid without lock */

View solution in original post

0 Kudos
3 Replies
659 Views
neojung
NXP Employee
NXP Employee

Hello Lukas,

Yes, the UART_RX_buffer is aligned to 16 bytes but after I divided the region like below, the issue was fixed and maybe the root cause is SMPU doesn't support duplicated region.

Thank you for your help!

Best regards,

Neo

    /* Region 0:  All internal SRAM of 768KB */

    SMPU_1.RGD[0].WORD0.R = 0x40000000;  /* Region start addr- start of SRAM */

    SMPU_1.RGD[0].WORD1.R = 0x400006CF;  /* Region end addr- end of SRAM  */

    SMPU_1.RGD[0].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[0].WORD3.R = 0x00000000;  /* Region cacheable: Cache Inhibit=0*/

    SMPU_1.RGD[0].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[0].WORD5.R = 0x00000001;  /* Region is valid without lock */

    /* Region 1:  Shared data 16 bytes long inside SRAM, cache inhibited */

    SMPU_1.RGD[1].WORD0.R = 0x400006D0; /* Reg start addr*/

    SMPU_1.RGD[1].WORD1.R = 0x400006EF; /*Region end */

    SMPU_1.RGD[1].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[1].WORD3.R = 0x00000002;  /* Region cacheable: Cache Inhibit=2*/

    SMPU_1.RGD[1].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[1].WORD5.R = 0x00000001;  /* Region is valid without lock */

    SMPU_1.RGD[2].WORD0.R = 0x400006F0;  /* Region start addr- start of SRAM */

    SMPU_1.RGD[2].WORD1.R = 0x400BFFFF;  /* Region end addr- end of SRAM  */

    SMPU_1.RGD[2].WORD2.FMT0.R = 0xFFFFFFFF; /* ALL masters can read/write */

    SMPU_1.RGD[2].WORD3.R = 0x00000000;  /* Region cacheable: Cache Inhibit=0*/

    SMPU_1.RGD[2].WORD4.R = 0x00000000;  /* PID not included in region eval. */

    SMPU_1.RGD[2].WORD5.R = 0x00000001;  /* Region is valid without lock */

0 Kudos
658 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

copied from RM (page 515):

pastedImage_0.png

pastedImage_2.png

Lukas

0 Kudos
658 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

is the UART_RX_buffer aligned to 16 bytes?

Start address and end address of memory region must be aligned to 16 bytes - last four bits in WORD0 and WORD1 are not writeable. I guess that this could be the root cause because setting of CI bit in WORD3 should be enough.

Regards,

Lukas