Hi Team,
We are using T2080QDS reference board as a base for developing our customized board. When I see the memory map of the reference board, all the addresses are provided in 36 bit. But as our OS support 32 bit addressing. We want U-Boot also to use 32 bit addressing. Keeping this in mind we prepared a memory map( Attached with this email). Now I have some confusion about these macros below:
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Reference board macro's for PCIE controller 1
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
As I see from the above macro definition the MEM_PHYS is 36 bit and the MEM_VIRT(TLB )entry is 32 bit virtual address and MEM_BUS is again 32 bit address , which according to my understanding overlap with the DDR memory map address(But I think as the reference board maps 2GB DDR only in U-BOOT that should be fine).
If I want to change the above macros according to our memory map(attached with this email), then will the below definition below will work:
/*For SVC */
#ifdef SVC_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xC0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xC0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xC00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xE0000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xE00000000ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#endif
Please help in entering the correct values for these macros according to our memory map.
Thanks & Regards
Manish Raturi
CONFIG_SYS_PCIE?_MEM_BUS macro defines the base address of the region
as it is seen on the PCI bus. This macro is used in PCIe ATMU initialization,
the size of the corresponding bus address depends on CONFIG_SYS_PCI_64BIT, see include/pci.h
The base address of the bus region as seen by the local
CPUs is defined by CONFIG_SYS_PCIE?_MEM_PHYS. Therefore, you cannot
eliminate any overlap in the local memory map by playing with
CONFIG_SYS_PCIE?_MEM_BUS macro.
If the question is, if a ready configuration for u-Boot with all
peripherals mapped to physical addresses below 4G exists, the answer
is no. To see if your configuration is valid, try it on your board.
Have a great day,
Platon
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