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mpc8313 elbc different bank accesses conflict

Question asked by shaojie wang on Jan 26, 2016
Latest reply on Jan 27, 2016 by shaojie wang

Dear expert.


In my design, the elbc bank 0 interfaces with the boot nor flash, bank 2 and band 3 interface with two FPGAs, working in the UPM mode. Bank 2 support DMA burst read and write, while Bank 3 does not support burst transfer.


When the Bank 2 or Bank 3 was accessed alone,(that is to say, when access to Bank 2, the Bank3 idle, and access to Bank 3, the Bank 2 idle.) the system runs ok. However, when both banks were accessed, the CPU would reset, and the RSR register value is 0x13.


So I wonder what the reason is, and how to solve it.



Expects for your response, Thanks.