mpc8313 elbc different bank accesses conflict

[rettozero]

Dear expert.

In my design, the elbc bank 0 interfaces with the boot nor flash, bank 2 and band 3 interface with two FPGAs, working in the UPM mode. Bank 2 support DMA burst read and write, while Bank 3 does not support burst transfer.

When the Bank 2 or Bank 3 was accessed alone,(that is to say, when access to Bank 2, the Bank3 idle, and access to Bank 3, the Bank 2 idle.) the system runs ok. However, when both banks were accessed, the CPU would reset, and the RSR register value is 0x13.

So I wonder what the reason is, and how to solve it.

Expects for your response, Thanks.

[r8070z · Accepted solution]

Have a great day,

What do you mean as "bank is idle" and "both banks were accessed"? The MPC8313 cannot access 2 eLBC banks simultaneously. The eLBC banks share the package pins. Only one eLBC bank can be active. Correspondingly only one LCSn can be assigned when there is access on the local bus. Ensure that external device connected to any LCSx frees the local bus when its LCSx is not assigned (i.e. when its LCSn is high).

Also banks can share the UPM. If bank2 and bank3 need for different UPM patterns ensure that they uses different UPMs (MPC8313 eLBC has 3 UPMs).

The RSR (Reset Status Register) captures various reset events in the device. This register returns to its reset value only when power-on reset occurs.

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[rettozero]

Sorry for my poor english.

the problem has been solved.

I raise up up the LCLK from 41.625MHz to 66MHz. the error not happened.

I know what you mean.

rettozero@aliyun.com