We have a custom board based on iMX6 quad core processor. It is designed to boot from eMMC, boot setting is from eFuses.
Processor: IMX6 Quad, revision : C
eMMC : MTFC16GJDEC-4M IT ( eMMC v4.41)
uSDHC port : USDHC3
SRC Boot Mode Register 1: 0x00005060
SRC Boot Mode Register 2: 0x30000011
We see majority of boards boots as designed. But there are random failures on one or two boards per hundred( 1 to 2% only).
We read the system SRC boot mode registers.Its readings are same for both the working and non-working boards.
The following signals from i.MX6 are captured for working and non working boards and is as below.
- POR_N ( reset pin)
- SD3_CLK ( clock to eMMC)
- SD3_CMD (CMD line to eMMC)
The waveforms of both working and non working boards are as below
Non Working Board Waveforms:
I expect SD3_CLK to toggle at 347.22 KHz( or 400KHz) as IMX6 attempts to boot. After initial CMD exchange between eMMC this clock should switch to 20MHz.
We can see this happen working in correct boards.
In non-booting boards after POR, CLK line stays high for around 16mS and then goes low, its not toggling then and IMX6 is moving to serial downloader mode.
I tweaked the Boot Mode pin settings to serial downloader mode, and observed that SD3_CLK is not changing at all.
This makes me feel that, i.MX6 understands that eMMC is the boot device and attempts to boot from eMMC. But it fails to complete the boot process..???
I extended POR_N so that if the booting problem was due to the timing deviation of internal 200KHz oscillator, it should go away, but there was no luck.
Any help to understand what is happening is really appreciated!!
Few questions came to my mind are :
(A) : Is there a register or memory location that I can access from MFG tool uboot to understand from which stage ( as in fig 8-10,fig 8-11 of reference manual) the booting rolled from eMMC to serial downloader mode.
(B): I went through the application note (TN-29-18: Booting from Embedded MMC e-MMC Device s Supporting MMCA Specification ver.4.3 )from micron. So I was expecting CSD3_CMD line to be held LOW for atleast 74 SD3_CLKs. So any clue where I am wrong? Is there a documentation stating what happens during the boot attempt of i MX6 from eMMC?
(C) Is IMX6 expecting any pattern in the SD3_DATA0 to SD3_DAT7 while SD3_CLK makes its first transition from HIGH to LOW ? And , probably that may be the reason why SD3_CLK stops to make any toggling??
(D) Any directions that can be helpful to understand the issue?
Thanks in advance.