Current customer questions:
Just to make sure I understand everything correctly, can you confirm that I should be referencing the T1040 documentation for information on the SDHC_CLK_SYNC_IN/OUT signals? If so, it seems like they are required for DDR50 mode and should be hooked up. Is this correct?
Also, can you confirm that the SDHC_VS and SDHC_CMD/DAT0/DAT123_DIR signals are supported as described in the T1040 documentation? They are mentioned in the T2080 RM, but not in its specifications or design checklist. If they are supported, can you tell me the logic sense of the SDHC_xx_DIR signals (i.e., which direction corresponds to logic low and which to logic high)?
These questions arise from this previous Service Center thread:
Answers from design:
1) Why SDHC_CLK_SYNC_OUT and SDHC_CLK_SYNC_IN signals are not mentioned in the T2080 Data Sheet and AN4804 - QorIQ T2080 Design Checklist, but are present in the RM?
A: These two signals should be removed from the RM. It was a mistake in the RM. Having said that, it should be the same as T1040 and it works. However, we are not going to make any change to HW spec and so on. It is just too late and expensive. Customers can use the DDR50 mode.
2) Was the DDR50 operation verified with SDHC_CLK_SYNC_OUT and SDHC_CLK_SYNC_IN signals?
A: T208QDS board with a SPF-28075 adapter was used to validate the DDR50 mode. Please refer to the attached schematics.