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I.MX6SX LPDDR2 boot fail?

Question asked by CY Hung on Jan 3, 2016
Latest reply on Jan 4, 2016 by Yuri Muhin

My board's CPU is an i.MX6SX with LPDDR2 (Micron MT42L128M32D1GU-25).

I use MX6SX_MMDC_LPDDR2_register_programming_aid_v0.5.xlsx to generate a LPDDR2 script,

then use ddr_stress_tester_v2.30 to calibration the LPDDR2 script on my board successfully.

To transfer the LPDDR2 script into imximage.cfg and build, but I can not boot my board from U-Boot.

Is the LPDDR2 script still incorrect or other cause?

 

//============================================================================= 

//init script for i.MX 6SX LPDDR2 

//============================================================================= 

// Revision History 

// v05 

//============================================================================= 

 

wait = on 

//============================================================================= 

// Disable WDOG

//============================================================================= 

//setmem /16 0x020BC000 = 0x30

 

//============================================================================= 

// Enable all clocks (they are disabled by ROM code) 

//============================================================================= 

setmem /32 0x020C4068 = 0xFFFFFFFF

setmem /32 0x020C406C = 0xFFFFFFFF

setmem /32 0x020C4070 = 0xFFFFFFFF

setmem /32 0x020C4074 = 0xFFFFFFFF

setmem /32 0x020C4078 = 0xFFFFFFFF

setmem /32 0x020C407C = 0xFFFFFFFF

setmem /32 0x020C4080 = 0xFFFFFFFF

 

// For A9/M4 shared access 

//setmem /32 0x0207C000 = 0x77777777

//setmem /32 0x0217C000 = 0x77777777

//setmem /32 0x0227C000 = 0x77777777

 

// setmem /32 0x020C4018 = 0x00260324 //DDR clk to 400MHz

 

//============================================================================= 

// IOMUX 

//============================================================================= 

//DDR IO TYPE: 

setmem /32 0x020E0618 = 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

setmem /32 0x020E05FC = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE

 

//CLOCK: 

setmem /32 0x020E032C = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P

 

//ADDRESS: 

setmem /32 0x020E0300 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

setmem /32 0x020E02FC = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

setmem /32 0x020E05F4 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_ADDDS

 

//Control: 

setmem /32 0x020E0340 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

setmem /32 0x020E0320 = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

setmem /32 0x020E0310 = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0

setmem /32 0x020E0314 = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1

setmem /32 0x020E0614 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_CTLDS

 

//Data Strobes: 

setmem /32 0x020E05F8 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

setmem /32 0x020E0330 = 0x00003028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P

setmem /32 0x020E0334 = 0x00003028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P

setmem /32 0x020E0338 = 0x00003028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P

setmem /32 0x020E033C = 0x00003028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P

 

//Data: 

setmem /32 0x020E0608 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE

setmem /32 0x020E060C = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B0DS

setmem /32 0x020E0610 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B1DS

setmem /32 0x020E061C = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B2DS

setmem /32 0x020E0620 = 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B3DS

 

setmem /32 0x020E02EC = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

setmem /32 0x020E02F0 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

setmem /32 0x020E02F4 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

setmem /32 0x020E02F8 = 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

 

//============================================================================= 

// DDR Controller Registers 

//============================================================================= 

// Manufacturer: Micron

// Device Part Number: MT42L128M32D1

// Clock Freq.:  400MHz

// Density per CS in Gb:  4

// Chip Selects used: 1

// Total DRAM density (Gb) 4

// Number of Banks: 8

// Row address:     14

// Column address:  10

// Data bus width 32

//============================================================================= 

 

setmem /32 0x021B001C = 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up

 

setmem /32 0x021B085C = 0x1B4700C7 // MMDC0_MPZQLP2CTL, LPDDR2 ZQ params

 

setmem /32 0x021B0800 = 0xA1390003  // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

 

setmem /32 0x021B0890 = 0x00380000 // MMDC0_MPPDCMPR2, CA bus absolute delay

 

setmem /32 0x021B08B8 = 0x00000800  // DDR_PHY_P0_MPMUR0, frc_msr

 

//###################################################### 

//calibration values based on calibration compare of 0x00ffff00: 

//Note, these calibration values are based on Freescale's board 

//May need to run calibration on target board to fine tune these  

//###################################################### 

 

//DATA TRACE READ DELAYS: 

setmem /32 0x021B081C = 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3

setmem /32 0x021B0820 = 0x33333333 // DDR_PHY_P0_MPRDQBY1DL3

setmem /32 0x021B0824 = 0x33333333 // DDR_PHY_P0_MPRDQBY2DL3

setmem /32 0x021B0828 = 0x33333333 // DDR_PHY_P0_MPRDQBY3DL3

 

//DATA TRACE WRITE DELAYS: 

setmem /32 0x021B082C = 0xF3333333 // DDR_PHY_P0_MPWRQBY0DL3

setmem /32 0x021B0830 = 0xF3333333 // DDR_PHY_P0_MPWRQBY1DL3

setmem /32 0x021B0834 = 0xF3333333 // DDR_PHY_P0_MPWRQBY2DL3

setmem /32 0x021B0838 = 0xF3333333 // DDR_PHY_P0_MPWRQBY3DL3

 

// DUTY CYCLE ADJUST: 

setmem /32 0x021B08C0 = 0x2492244A // Change dutycycle Byte1, Byte2

 

// READ DQS DELAY: 

setmem /32 0x021B0848 = 0x42444646  // MPRDDLCTL PHY0, 0x3E42424A

 

// WRITE DQS DELAY: 

setmem /32 0x021B0850 = 0x3A3C3C3A // MPWRDLCTL PHY0, 0x38363832

 

// DQS GATE DELAY: 

setmem /32 0x021B083C = 0x20000000 // MPDGCTRL0 PHY0, gate delay not used in LPDDR2, disable

setmem /32 0x021B0840 = 0x00000000 // MPDGCTRL1 PHY0

 

// Complete calibration by forced measurement: 

setmem /32 0x021B08B8 = 0x00000800  // DDR_PHY_P0_MPMUR0, frc_msr

 

setmem /32 0x021B000C = 0x33374133 // MMDC0_MDCFG0

setmem /32 0x021B0004 = 0x00020024 // MMDC0_MDPDC

setmem /32 0x021B0010 = 0xB6B00A42 // MMDC0_MDCFG1

setmem /32 0x021B0014 = 0x00000093 // MMDC0_MDCFG2

setmem /32 0x021B0018 = 0x00001748 // MMDC0_MDMISC

setmem /32 0x021B002C = 0x0F9F26D2 // MMDC0_MDRWD; recommend to maintain the default values

setmem /32 0x021B0030 = 0x009F0D10 // MMDC0_MDOR

setmem /32 0x021B0038 = 0x00190779 // MMDC0_MDCFG3LP

setmem /32 0x021B0008 = 0x12272000 // MMDC0_MDOTC

setmem /32 0x021B0040 = 0x0000004F // CS0_END

setmem /32 0x021B0000 = 0x83110000 // MMDC0_MDCTL

 

 

// Mode register writes 

setmem /32 0x021B001C = 0x003F8030 // MMDC0_MDSCR, MR63 write, CS0

setmem /32 0x021B001C = 0xFF0A8030 // MMDC0_MDSCR, MR10 write, CS0

setmem /32 0x021B001C = 0x82018030 // MMDC0_MDSCR, MR1 write, CS0

setmem /32 0x021B001C = 0x04028030 // MMDC0_MDSCR, MR2 write, CS0

setmem /32 0x021B001C = 0x02038030 // MMDC0_MDSCR, MR3 write, CS0

 

setmem /32 0x021B001C = 0x003F8038 // MMDC0_MDSCR, MR63 write, CS1

setmem /32 0x021B001C = 0xFF0A8038 // MMDC0_MDSCR, MR10 write, CS1

setmem /32 0x021B001C = 0x82018038 // MMDC0_MDSCR, MR1 write, CS1

setmem /32 0x021B001C = 0x04028038 // MMDC0_MDSCR, MR2 write, CS1

setmem /32 0x021B001C = 0x02038038 // MMDC0_MDSCR, MR3 write, CS1

 

//FINAL SETTINGS: 

setmem /32 0x021B0020 = 0x00001800 // MMDC0_MDREF

setmem /32 0x021B0818 = 0x00000000 // DDR_PHY_P0_MPODTCTRL

 

setmem /32 0x021B0800 = 0xA1310003  // DDR_PHY_P0_MPZQHWCTRL, enable automatic HW ZQ calibration.

setmem /32 0x021B0004 = 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled

setmem /32 0x021B0404 = 0x00010106  //MMDC0_MAPSR ADOPT power down enabled

 

setmem /32 0x021B001C = 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

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